Diplomarbeit Development of Fractional-N Based Frequency Synthesizers for a 5,2 GHz Radio Front-End Ausgef¨ uhrt zum Zwecke der Erlangung des akademischen Grades eines Diplom-Ingenieurs unter Leitung von Dipl.-Ing. Robert Langwieser und Ao. Univ.Prof. Arpad L. Scholtz E389 Institut f¨ ur Nachrichtentechnik und Hochfrequenztechnik eingereicht an der Technischen Universit¨at Wien Fakult¨atf¨ ur Elektrotechnik und Informationstechnik von Michael J. Glatz 9925361 Dreipappelstr. 24, 2700 Wr. Neustadt Wien, September 2007
Transcript
Diplomarbeit
Development of Fractional-N BasedFrequency Synthesizers for a 5,2GHz
Radio Front-End
Ausgefuhrt zum Zwecke der Erlangung des akademischen Grades eines
Diplom-Ingenieurs unter Leitung von
Dipl.-Ing. Robert Langwieser
und
Ao. Univ.Prof. Arpad L. Scholtz
E389
Institut fur Nachrichtentechnik und Hochfrequenztechnik
eingereicht an der Technischen Universitat Wien
Fakultat fur Elektrotechnik und Informationstechnik
von
Michael J. Glatz
9925361
Dreipappelstr. 24, 2700 Wr. Neustadt
Wien, September 2007
Abstract
In telecommunications, data transmission from transmitter to receiver utilizesspecific techniques. Some of these perform a shift of the information signal tothe preferred carrier frequencies to obtain suitable propagation conditions. Forwireless transmission, the frequency spectrum is divided to assign each servicepermitted frequency bands. Therefore, flexible carrier frequencies become a ne-cessity. Specialized oscillators, called frequency synthesizers, provide adjustableoutput frequencies. They enable transmitter and receiver systems to allocatetheir assigned transmission bands.
This work describes the development of two fractional-N based frequency syn-thesizers for different center frequencies. The concept is elaborated, and all com-ponents are described in detail. The developed synthesizer control software isexplained, and finally performance measurements of both synthesizers are pre-sented.
i
Kurzfassung
In der Telekommunikation werden zur Datenubertragung zwischen Sender undEmpfanger verschiedene Techniken angewandt. Dabei wird das Informations-signal in gewissen Fallen zu Tragerfrequenzen hin verschoben, um entsprechendeAusbreitungsbedingungen zu erhalten. In der drahtlosen Kommunikation werdenverschiedenen Diensten jeweils erlaubte Frequenzbander aus dem Funkfrequenz-spektrum zugewiesen. Um diese Frequenzbander auswahlen zu konnen, werdenflexible Tragerfrequenzen benotigt.
Sender und Empfanger benotigen zur Auswahl der zugewiesenen Frequenz-bander spezielle Oszillatoren mit veranderlichen Ausgangsfrequenzen. Man sprichtvon Frequenzsynthesizern.
Diese Arbeit beschreibt die Entwicklung zweier Fractional-N Frequenzsynthe-sizer mit unterschiedlichen Mittelfrequenzen. Dabei wird auf das Konzept, dieEinzelkomponenten, die Softwaresteuerung und meßtechnische Erfassung der Re-sultate eingegangen.
ii
Contents
Introduction 1
1 System Concept 31.1 Local Oscillators in Radio Systems . . . . . . . . . . . . . . . . . 3
1.1.1 Frequency Conversion and Channel Spacing . . . . . . . . 31.1.2 Radio Test and Measurement System . . . . . . . . . . . . 6
Frequency synthesis oscillators, which in this work will be termed frequency syn-thesizers or synthesizers for simplicity, are an integral element of frequency con-version. In one or multiple steps, the baseband spectrum is shifted towards acarrier frequency. While the intermediate frequency is fixed for technological rea-sons, the output frequency is required to be flexible in many applications. In thiscase, frequency synthesizers can be used to provide adjustable frequencies for theconversion.
This diploma thesis focuses on two frequency synthesizers which serve as firstand second LO1 for a test and measurement system, with center frequencies of1087, 5 MHz and 4252, 5 MHz, respectively. Both are designed and constructedspecifically for this application.
In Chapter 1 the concept of a radio system is outlined in which the presentedsynthesizers will be used. It is emphasized which components of the radio systemare investigated in this thesis.
The theory of PLL2 synthesizers is reviewed in Chapter 2 to render the opti-mum synthesizer concept for the intended application. An according integratedcircuit, the ADF4153, that will be used for the composition of both LO1 andLO2, is presented. A comparison chart of PLL integrated circuits informs aboutthe general performance level of devices available on the market at the time ofcomponent selection. An important task, the design of the PLL loop filter, is ad-dressed. With regard to the realization of both synthesizers, the passive secondorder loop filter topology is emphasized.
The PLL principles are applied to design a synthesizer with 1087, 5 MHzcenter frequency in Chapter 3. All components are presented and discussed indetail, including the VCO3, the RF4 amplifier, the reference oscillator, and theloop filter setup. The interaction of all these components and additional circuitryare combined in the provided schematics and result in the depicted RF layout.
Similarly, in Chapter 4 a synthesizer for 4252, 5 MHz is presented, based onthe foundations emphasized in Chapter 2. Again the choice of all componentsand the RF circuitry are discussed.
1Local Oscillator2Phase-Locked Loop3Voltage Controlled Oscillator4Radio Frequency
1
In the next step, a microcontroller approach to set the output frequency andother parameters of the PLL circuit is described in Chapter 5. Program codefor uploading data to the PLL is shown. When connected to a synthesizer PCB5
from Chapter 3 or Chapter 4, the controller makes the setup fully operational.With the completed synthesizer setup, output spectrum measurements for
both synthesizers have been performed, which is covered in Chapter 6. Varioussynthesizer settings are investigated. Thus the synthesizer function is confirmedand the performance can be classified.
Finally, the diploma thesis is summed up.
5Printed Circuit Board
2
Chapter 1
System Concept
To begin, this chapter explains the task of frequency synthesizers in radio sys-tems. The synthesizer implementations are required to have a certain amount offlexibility, but high performance is emphasized for the use in radio systems.
For this work, the frequency synthesizers may be viewed as autonomous sub-systems, as their RF outputs represent standardized interconnections and thesynthesizers will also housed in dedicated enclosures. Thus it is possible to focuson the synthesizer subsystems alone, but with emphasis to their role in the entiresystem. Section 1.2 covers the synthesizer composition.
1.1 Local Oscillators in Radio Systems
Radio signals occupy dedicated bands of the frequency spectrum. These bandsare characterized by their upper and lower cut-off frequencies, or equally, by theirbandwidth and center frequency. Within that frequency band, a given radiosystem may transmit with a significant power spectral density. The receiveraccordingly picks this band out of the radio spectrum to process it and decodethe sent message.
1.1.1 Frequency Conversion and Channel Spacing
In their original form, telecommunication signals either have lowpass character,with vanishing spectrums at points greater than a cut-off frequency1, or pass-band character with bias to near-DC2 values. However, to allocate the assignedfrequency band for obtaining suitable transmission conditions, both transmitterand receiver of the radio system have to perform a frequency conversion. Thisprocess can be realized by a component called mixer. An ideal mixer can bemodeled as a multiplier as seen in Figure 1.1.
1With respect to real-valued signals, the absolute frequency value is considered.2Direct Current, i.e. zero frequency
3
1.1 Local Oscillators in Radio Systems
1f
2f
21 ff
21 ff
Figure 1.1: Ideal Mixer.
Let us assume two sinusoidal input signals for the multiplier with frequenciesf1 > 0 and f2 > 0, respectively. It can be shown that the output frequencies thenare f1 + f2 and |f1 − f2|, without the presence of either f1 nor f2. This propertydescribes the wanted frequency conversion.
Now one sinusoidal input signal of the mixer is replaced by the messagesignal in passband domain with center frequency f1. When ideally multiply-ing this passband signal with a second signal containing only a single frequencycomponent fLO, the multiplication will yield another passband signal, which is afrequency-shifted version of the message signal by amount of fLO. Thus f1 + fLO
becomes the carrier frequency. The multiplier has performed an upconversion(cf. Figure 1.2), and the signal is now ready for transmission. The task of gener-ating fLO is done by the local oscillator.
LO
Power Spectral Density
f
1f LOff1LOf
Figure 1.2: Signal Spectra for Upconversion.
The same principle is applied for the downconversion process (Figure 1.3),i.e. the frequency shift from RF to baseband at the receiver. After passbandfiltering of the wanted signal for image rejection and blocking prevention, thereceived passband signal is fed into a mixer. The receiver’s local oscillator is tunedto fLO. According to the principle described above, the resultant spectra aresituated at the sum and difference frequencies of the mixer inputs. As depicted,we obtain spectra in the original passband location at f2 − fLO and a versionshifted to f2 + fLO, which can be omitted by filters.
The conversion process may be done in one or multiple steps. The quality ofavailable electronic filters and active components has physical limits, that is why
4
1.1 Local Oscillators in Radio Systems
LO
Power Spectral Density
f
LOff2 2fLOf LOf2 LOff2
Figure 1.3: Signal Spectra for Downconversion.
in some cases it is wiser to perform the frequency conversion in multiple steps.For heterodyne3 frequency conversion, the way from baseband to carrier frequencyand back leads over at least one intermediate frequency IF. Every conversion stepis achieved by components specialized for their working frequency range. Forexample, the local oscillators in a two-step heterodyne system are termed LO1and LO2.
Many radio systems split up a relatively broad transmission band into severalchannels, which occupy adjacent frequency bands. Usually the channels have
f
......
CfCfPower Spectral Density
Figure 1.4: Channel Raster.
equidistant center frequencies and are of identical bandwith. The distance be-tween two adjacent channel center frequencies ∆fC is the required fundamentalinterval for channel selection. See Figure 1.4 for illustration.
If the LO frequency is adjustable, it can either be set to arbitrary or only tospecific values within the supported frequency range. For example, the possibleLO output frequencies are equidistant in steps of fstep. In this case, the condition
∆fC = n · fstep with n ∈ N (1.1)
must be satisfied for successful channel selection.
3as opposed to the homodyne principle which only performs one conversion step
5
1.1 Local Oscillators in Radio Systems
1.1.2 Radio Test and Measurement System
This diploma thesis is intended to supply the local oscillator technology for aRapid Prototyping radio transmitter and receiver system. To meet the specificdemands of this project, two different oscillators, which will be realized as fre-quency synthesizers, are required.
LO1 LO2
LO1 LO2
BPF BPF BPF
BPFBPFBPF
Power AmpMixer
MixerMixer
Mixer
LNAAmplifier
1087,5 MHz 4252,5 MHz
1087,5 MHz 4252,5 MHz
Rx Antenna
Tx Antenna
5,2 GHz
Radio Link
TRANSMITTER
Signal
Processing
Signal
Processing
RECEIVER
140 MHz
140 MHz
Figure 1.5: Proposed Transmitter and Receiver (1 Channel).
The system consists of transmitter and receiver, each with heterodyne fre-quency conversion utilizing two local oscillators, with center frequency 1087,5 MHzfor LO1 and 4252,5 MHz for LO2. The basic radio system in Figure 1.5 uses oneantenna at the transmitter and also one antenna at the receiver. The proposedsystem in contrast uses eight transmitters and eight receivers, each with dedicatedantennas (Figure 1.6). The eight transmission antennas can be driven indepen-dently. With this setup, the system performance can be significantly enhanced,and similar improvement is possible on the receiver side. The overall setup repre-sents an 8×8 - MIMO4 system with a total antenna count of 16. Importantly, alleight parallel transmitter frontends use the same LO frequencies, i.e. the overalltransmitter still requires only LO1 and LO2 synthesizers, albeit each now witheight uniform outputs. The same holds true for the receiver. To recapitulate,the proposed 8 × 8 - MIMO system in total requires two local oscillators with
4Multiple Input Multiple Output
6
1.1 Local Oscillators in Radio Systems
1087,5 MHz center frequency and also two with 4252,5 MHz. These synthesizersare object of this diploma thesis.
Signal
Processor
LO2LO1Sync
D
A
1087,5 MHz 4252,5 MHz
Signal
Processor
LO2LO1Sync
A
D
Receiver
Radio-Front-End
1087,5 MHz 4252,5 MHz
5,2 GHz
Radio Link
8-Antenna-Array
Transmitter
Radio-Front-End
8-Antenna-Array
Figure 1.6: System for 8 × 8 - MIMO.
Chapter 3 addresses LO1 with f0 = 1087, 5 MHz and Section 3.1 deals withits exact requirements. For LO2 generating f0 = 4252, 5 MHz, Chapter 4 explainsthe specific requirements in Section 4.1.
The most important requirement for both synthesizers is to feature low noiseRF output spectrums combined with a small frequency step size, without disre-garding the other demands.
7
1.2 Frequency Synthesizer Setup
1.2 Frequency Synthesizer Setup
This section shows the components of the synthesizer and their interaction. Thesecomponents are
- the main circuit board,
- the microcontroller, and
- the voltage supply.
The setup is depicted in Figure 1.7, where the main circuit board featuresconnectors for the RF output as well as the frequency reference signal inputand output. By using the microcontroller, the synthesizer RF output frequencyand other parameters can be programmed. A voltage supply provides multipleoutputs for the main circuit board and the microcontroller.
SMB
Main Circuit Board
Voltage Supply
PCB
Micro-
Controller3-Wire Interface
+3,0 V
+4,4 V
+5,0 V
+12,0 V
-12,0 V
DC
PC
RF OUT
REF IN
REF OUT
SMB
SMBD
C +12,0 V
Interface
Converter
JTA
G
+3,0 V
Figure 1.7: Frequency Synthesizer Components.
Below, the individual components are described in more detail.
1.2.1 Main Circuit Board
The PLL circuit is placed on the main circuit board (PCB). There is one PCB forthe 1087,5 MHz synthesizer and another PCB for the synthesizer that covers thegeneration of 4252,5 MHz. The circuit has subareas with different frequencies ofoperation, from 10 MHz at the reference oscillator to radio frequency (>1 GHzand >4,2 GHz respectively). The circuit elements found on either PCB include
8
1.2 Frequency Synthesizer Setup
- the 10 MHz reference oscillator,
- the PLL IC,
- the loop filter,
- the VCO,
- the RF prescaler5 and
- the RF output amplifier.
Figure 1.8 shows a block diagram that depicts the interaction of these compo-nents. By means of a selector, either the input from REF IN or the signal from
Loop
Filter
Reference
Oscillator
Selector
RF Output
Amplifier
Impedance
Buffer
RF
Prescaler
RF OUT
REF OUT
REF IN
DC Supply Voltage
Programming Interface
Main Circuit Board
RF Microstrip Line
PLL
IC
VCO
Figure 1.8: Block Diagram of the Main PCB.
the onboard reference oscillator is passed on to an impedance buffer. The outputof this buffer amplifier is present at the REF OUT output and the reference inputof the PLL IC. In combination with the loop filter, the PLL IC output generatesa control voltage at the VCO input. As reaction to this voltage, the VCO gener-ates an RF signal, and the output amplifier provides isolation between the PCB’sRF output and the VCO. A part of the VCO output power is directed back viathe RF prescaler to the PLL IC for frequency and phase comparison with thereference signal.
The programming interface receives data from the microcontroller for loadingthe PLL IC register set, while a DC voltage supply powers the circuits across thePCB.
5on the 4252,5 MHz PCB only
9
1.2 Frequency Synthesizer Setup
1.2.2 Microcontroller
The microcontroller or µC is situated on a dedicated PCB, and is connectedto the main circuit board via standard 3-wire-interface. The Texas Instruments
low-consumption controller MSP430F149 in a demo board setup is used to sendcontrol data to the PLL PCB. On the other hand, the µC can be linked to apersonal computer by means of a JTAG6 interface. Thus, it is possible to uploadnew program code and frequency data to the controller flash memory.
1.2.3 Voltage Supply
The voltage supply PCB provides five output voltages for the various componentson the main circuit board. Three linear voltage regulators provide DC outputsof 3,0 V, 4,4 V and 5,0 V. The +12 V rail is directly passed on to the mainPCB. In addition, one -12V DC output from a DC-DC converter is available.The PCB is designed to be used in conjunction with an 12 V DC supply thatfeatures adequate voltage ripple suppression and, if applicable, AC line filtering.Figure 1.9 shows a picture of the voltage supply PCB.
Figure 1.9: Picture of the Voltage Supply PCB.
6Joint Test Action Group, usual name for the IEEE 1149.1 standard PCB test access ports
10
Chapter 2
Phase-Locked Loop FrequencySynthesizers
PLL synthesizers are well suited to be used as local oscillators in radio systems.Frequency stability and channel spacing requirements can be realized adequately.
The following sections provide both general and more specific views on PLLsynthesizers, starting with basic operation principles. From Section 2.2, there ismore focus on the specific demands of this diploma thesis.
2.1 Principle of Operation
The PLL output gets phase-locked to a reference frequency, which is arranged bycomparing reference phase and actual output phase within a loop structure. Thephase-locked state, the locked-in state, is maintained through permanent com-parison. Deviations of the output compared to the reference are compensated bythe PLL, for example frequency drifts caused by fluctuations in part temperature.
2.1.1 Basic PLL Elements
Figure 2.1 depicts a PLL containing the basic elements: phase detector, loopfilter, VCO and reference oscillator.
The PLL aims for zero phase difference between the reference and the VCOoutput. To illustrate the principle of operation, assume a VCO output signal thatlags behind the reference by a phase amount of ∆θ > 0. This phase gap could beclosed if the VCO output frequency would be slightly raised, thereby reducing ∆θuntil ∆θ = 0. At this point the initial frequency rise should be undone, to finallyhave equal frequencies and zero phase difference at the phase detector inputs. Asimilar process could be invoked to cancel out ∆θ < 0 by temporarily loweringthe VCO frequency compared to the unaltered reference.
The state of∆θ(t) = 0 ∀t > t0
from a time point t0 is called locked-in because the frequency output is nowcoupled phase-locked to the reference oscillator. Note that only signals withequal frequency can have vanishing phase difference at all time points.
Phase Detector and Charge Pump
The phase detector is the element that compares the electric phases of the ref-erence voltage generated by the reference oscillator and the actual VCO output.Based on the phase difference, the phase detector creates a voltage or currentoutput that is led to the loop filter.
A prerequisite for phase comparison is exact or near equality of the inputfrequencies. If the input frequencies are too far apart, proper function is notpossible. For this reason a combined phase and frequency detector is preferred:It acts as a frequency detector for larger frequency deviations, thus seeking avanishing frequency difference. Then the phase detector mechanism is able to takeover and finally establish lock-in. This combined frequency and phase equalityapproach can be implemented as PFD1. The reference fref may be frequency-scaled prior to the PFD. However, the resulting actual frequency fPFD at thePFD input is proportional to fref .
Modern phase detectors mostly provide controlled bipolar current sources2 asan output, where ”bipolar” means that output currents can be sourced or sinked,depending on the direction of the intended frequency change. These currentsources are often referred to as charge pumps.
Loop Filter
Coming from the phase detector, the control pulses as a result of the phasecomparison can be short in time and therefore wide in bandwidth. The followingVCO essentially requires the DC and low frequency information contained in the
1Phase Frequency Detector2Traditional theory of phase detectors involves output voltage sources, which can be viewed
as duality to current sources in the sense of the Thevenin-Norton theorems. Current sourcesexhibit some advantages over voltage sources in this application and are therefore widely usedin the industry nowadays.
12
2.1 Principle of Operation
pulses at the control input. The DC component created by the pulses establishesequilibrium. Therefore only loop filters with low-pass behavior are considered.
Active loop filters rely on active circuits to achieve the filter transfer function3
Z(s), such as operational amplifiers in appropriate setups. These filters have thepossibility of supplying higher voltages to the VCO than the phase detector candeliver. This becomes important when VCOs requiring up to 20 V or more controlvoltage should be used. The disadvantages of the active loop filter are enhancednoise and more complexity, however.
Passive loop filters exclusively consist of passive components like resistorsand capacitors. While matching phase detector output and VCO control voltageranges are a prerequisite, this approach is preferred, because noise suppression isemphasized to maximize performance.
The number of poles in the transfer function Z(s) determines the loop filterorder. By its transfer function, the loop filter affects the open loop gain4 G(s) andtherefore has an impact on the PLL operation. The loop filter components de-termine lock time, phase margin, spur suppression and noise suppression. Theseparameters are not independent, and the designer can optimize those which aremost important in the given application. For example, while focusing on noisesuppression like in this diploma thesis, the phase margin must be monitored topreserve the PLL stability. Noise sources in a PLL are the reference oscillator,phase detector, loop filter and the VCO. If present, also frequency dividers con-tribute to the PLL noise. On the other hand, there are no lock time requirementsfor this thesis. In Section 2.3 a way to derive the component values of a passivesecond order loop filter is described in detail.
For phase detectors with charge pump output, the loop filter moreover hasthe task of converting the electric current from the charge pump into a voltageto control the VCO.
Voltage Controlled Oscillator
The VCO is the device that generates the RF output. The oscillation frequencyis variable and is determined by the VCO input control voltage. A control voltagerange is thereby translated into an output frequency range. This mapping is notnecessarily linear, but monotonic in nature. In the PLL, this device receives itscontrol voltage from the loop filter and generates an RF output accordingly. Aportion of the output power is fed back to the phase detector.
There are differences in the relative output frequency range5 and in the re-quired magnitude of the control voltage. VCOs with wider output frequencyrange are more tightly coupled to the control voltage and exhibit less inherentfrequency stability. For maximum performance, the VCO should be chosen withthe smallest output frequency range that meets the requirements. This property
3The argument s is the complex Laplace frequency variable4cf. Equation (2.16) in Section 2.35The output frequency range width is viewed in relation to the center frequency.
13
2.1 Principle of Operation
is also reflected in the data sheets, where otherwise similar VCO devices showdegraded performance for wider output frequency ranges.
When a passive loop filter is used, the control input voltage is effectively gen-erated by the phase detector output. To use the full frequency range of the VCO,the phase detector must be able to produce enough voltage at its output. Theideal VCO control input is a high impedance voltage input. Actual devices havea parasitic input capacitance that sometimes cannot be neglected, for examplewhen higher order passive loop filters are used.
Last but not least the output spectrum in the simple case of a DC controlvoltage is considered. Most emphasis is directed to the VCO noise. The secondand third harmonic of the output signal have considerable power, but filters canbe applied with relative ease to suppress the harmonics.
The properties and considerations stated above considerably reduce the num-ber of suitable VCOs for the application.
Reference Oscillator
The reference oscillator is the foundation for frequency synthesis and the deter-mining reference fref . Frequency drifts or inaccuracies of this element will betranslated to the output inevitably. The reference frequency fref is in most casesfixed or only slightly altered to perform frequency fine tuning. Typically, ultra-stable oscillators provide very little tuning range in favor of frequency stability.
Crystal-based oscillators can deliver tight frequency tolerances, depending onthe crystal plane cut and the mechanical surroundings. High performance refer-ence oscillators are designed to minimize the impact of the ambient temperatureon the fundamental frequency. Their massive metal package, which includes thecrystal and electronics, is kept at constant temperature by means of controlledoven heating, thus the acronym OCXO6.
2.1.2 Extended System with Frequency Divider
Using a frequency divider in the loop between the VCO’s RF output and the PFDinput, it is possible to synthesize much higher frequencies at the PLL output thanthe reference frequency.
The frequency divider translates the RF output frequency fout to the phasedetector input fPFD by a factor of 1
N. Conversely, the output frequency is N
times the phase detector input frequency:
fout = fPFD · N (2.1)
This is fundamental, because N can be used to modify the output frequency. Thisphase-locked loop synthesis is an indirect frequency synthesis7, where different
6Oven Controlled X-tal (Crystal) Oscillator7in contrast, direct frequency synthesis uses digital signal processing
14
2.1 Principle of Operation
)(sZ
N
Reference Oscillator Loop Filter VCO
Frequency Divider
Phase Detector
dt
df out
out
outKi
reff Nout /
ref
Figure 2.2: PLL Frequency Synthesizer Elements.
output frequencies can be derived from a single reference frequency with thesame relative frequency stability.
The benefits of extending the basic PLL with a frequency divider as shown inFigure 2.2 are the abilities to
- phase-lock unequal reference and output frequencies,
- enable adjustable output frequencies for a fixed reference, if the divisionfactor is programmable.
Both reasons apply for the synthesizer in this diploma thesis: To have a fixed10 MHz reference and a programmable output in the range from 1037,5 MHz to1137,5 MHz at the same time (example for the 1087,5 MHz synthesizer).
Together, the division factor N and the PFD input frequency fPFD determinethe output frequency. Whether N is an integer alone or has an additional frac-tional part has an effect on the possible outputs fout and other attributes of thePLL.
Integer-N Division
When the divider factor N can assume exclusively integer values, the step betweentwo adjacent output frequencies is because of (2.1)
fstep,int = fPFD (2.2)
This characteristic frequency step, the step size, in the case of the integer-N PLL,cannot be made small while maintaining a reasonable high comparison frequencyfPFD. To achieve best spectral purity of the output, fPFD must be as high aspossible within the specifications of the phase detector. But with higher fPFD,the step size grows accordingly. When both high performance (and thus a highcomparison frequency) and small step size are called for, a different approachrather than integer-N division should be considered.
15
2.1 Principle of Operation
For fixed-frequency synthesizers, the integer-N solution may yield fine results,however. The only drawback then would be a relatively coarse spacing of thepossible output frequencies, as outputs can occur only at integer multiples offPFD.
Fractional-N Division
The synthesizers in this diploma thesis aim for maximum spectral purity of theoutput while providing a significantly smaller step size than the comparison fre-quency. Moreover, with the suggested 10 MHz reference oscillator, the requiredcenter frequencies of 1087,5 MHz and 4252,5 MHz could not be established withan integer division factor N , since both 1087,5
10and 4252,5
10are not integers.8
These circumstances demand a solution, which comes in the form of fractional-Ndivision. This concept realizes a division factor of the form
Ntot = N +K
F(2.3)
Hence, the new average division factor consists of an integer part N and afractional part K
F. K and F by themselves are integers with K > 0 and F > 0,
where K is referred to as the fraction and F as the modulus. Substituting Ntot
for N , Equation (2.1) becomes
fout = fPFD · Ntot (2.4)
Since the smallest increment for Ntot with these preconditions is 1
F, the step size
of the fractional-N PLL becomes
fstep,frac =fPFD
F(2.5)
The improvement over the integer-N division in this aspect is essential. Evi-dently the number of possible center frequencies is multiplied by the factor F incomparison to standard integer-N division.
The convenience of the fractional-N PLL has a price, which has its foundationin a new mode of operation: The average division factor Ntot is realized by alter-nating between integer factors in a time pattern that depends on the fractionalparameters K and F . A sophisticated method for this purpose uses a fractionalinterpolator to process these variables and generate an output to be used togetherwith the integer factor N . Even though this effort is often made, some configu-rations of the parameters K and F cause degraded performance with respect tothe output spectrum. The reason is that the fractional-N operation introducestemporary deviations from equilibrium, which eventually manifest themselves in
8The only solution for exactly realizing the center frequencies would be to slightly ”pull”the reference oscillator frequency (i.e. fref 6= 10 MHz), but this approach would not addressthe problem of the large step size.
16
2.1 Principle of Operation
unwanted spurious lines in the output spectrum. Therefore, the quality of theoutput spectrum in this case may depend on the center frequency.
The key advantage of the fractional-N approach is the benefit of utilizing highcomparison frequencies fPFD for best noise performance while not disregardingthe step size requirements.
2.1.3 Synthesizer Realization with a PLL IC
When building a PLL synthesizer, using a PLL IC may be considered. Thefollowing sections address possible consequences and potential benefits of usingthis device.
PLL IC
The PLL IC contains a crucial PLL element, the phase detector. Often thedector output is implemented as a ”charge pump” current source. The secondcomponent within the PLL IC is the programmable frequency divider that realizesN for integer-N or Ntot for fractional-N PLLs, respectively. To improve the lock-inprocess, some PLL ICs utilize a PFD instead of the basic phase detector.
The frequency divider is implemented using counters, where the programmablecounter variables determine the divison factor. Note that these circuits in CMOS9
technology only process timing information about the zero-crossings of the inputsignal, as this is sufficient to determine the frequency. In this way the inputbecomes a CMOS square wave clock signal to trigger digital counters, and theresult is a CMOS signal with fundamental frequency fPFD at one PFD input.For minimized timing jitter of the zero-crossings and thus better performance,the PFD reference input is preferably driven by a square wave signal source likethe reference oscillator used in this diploma thesis. Furthermore, the duty cycleof the square wave has an effect on the performance. A variation from the ideal50:50 duty cycle may cause degraded performance.
If required, the comparison input frequency can be scaled down prior to thePLL IC to extend the output frequency range. For this task, an external prescalerwith fixed integer division factor is preeminent. Secondly, many PLL ICs havefeatures for doubling or dividing the incoming reference oscillator frequency. Thefollowing sections investigate the impact of the frequency extension measures onthe formulas for the fractional-N PLL.
External Prescaler
Being a device with a fixed divison factor V , the prescaler is introduced into thephase-locked loop to increase the overall division factor between RF output and
9Complementary Metal-Oxide-Semiconductor
17
2.1 Principle of Operation
)(sZ
totN
Reference Oscillator
Loop Filter VCO
Frequency Divider
Phase Detector
R
DVNff totrefout
reff
PFDf
V
R
D
Frequency Scaler
Prescaler
outf
PLL IC
Figure 2.3: PLL Synthesizer with Prescaler.
phase detector.
fout = fPFD · Ntot · V = fPFD ·
(
N +K
F
)
· V (2.6)
A practical reason for using the prescaler is to lower the frequency at the RF inputof the divider Ntot. This allows to match the PLL IC, that has Ntot implemented,to VCOs of higher frequencies than the PLL IC originally would allow. In otherwords, the RF output is prescaled to match the PLL IC’s specifications. Withthis possibility, the prescaler is a very valuable tool. A side effect is the alteredstep size when using a prescaler V :
fstep,frac =fPFD
F· V (2.7)
This is easily understood as the smallest increment of the the overall divisionfactor is now V
F. Applying a prescaler factor V = 2 merely doubles the frequency
step size, which is no significant penalty for most applications.
Reference Frequency Doubling and Division
The following formula links the reference oscillator frequency fref and the phasedetector comparison frequency fPFD, where D is the frequency multiplicationfactor and R is the respective division factor.
fPFD = fref ·D
R(2.8)
This functionality may be available on the PLL IC to scale the incomingfrequency fref . An application would be to provide the phase detector with the
18
2.2 PLL IC Comparison
doubled reference frequency by setting D = 2 and R = 1 (neutral), thereforeimproving the PLL noise performance. The final results for a fractional-N PLLsynthesizer with prescaler V , reference frequency multiplier D, and divider R aresummarized below.
fout = fref ·
(
N +K
F
)
·DV
R(2.9)
fstep =fref
F·DV
R(2.10)
Typically, to evoke a frequency change, only N and K are modified while theother parameters of (2.9) and (2.10) remain constant. This guarantees a constantstep size fstep across the entire output frequency range.
2.2 PLL IC Comparison
This section shows the position of the ADF4153 Fractional-N Frequency Synthe-sizer by Analog Devices [4], that will be used throughout this diploma thesis, inrelation to market contenders.
A lot of performance potential resides in the PLL IC. To get the best results,a comprehensive product comparison will prove beneficial. Of course, first thepresupposed requirement of the RF bandwidth has to be satisfied. The remainingspecifications are the foundation to pick the best IC for the application.
Table 2.1 shows some possible choices for the synthesizer’s PLL IC. All modelsfeature a Σ-∆ fractional interpolator. The ADF models come from Analog Devices,the LMX contenders from National Semiconductor.
RF Bandwidth: The maximum RF operating frequency is particularly impor-tant. All shown models require an external frequency prescaler for the4252,5 MHz synthesizer, as long as no frequency doubler at the final RFoutput is used. Rather, the VCO output is frequency divided (for examplea division by 2) to suit the PLL IC’s input capability.
19
2.2 PLL IC Comparison
Maximum Comparison Frequency: In order to improve phase noise perfor-mance, higher values of fPFD are better. The LMX2471 from National
Semiconductor stands out in this category. On the other hand, given thefref = 10 MHz reference oscillator, some device has to apply frequencyscaling to establish higher fPFD. The ADF4153 has a built-in referencefrequency doubler.
Normalized Phase Noise: The actual phase noise depends on the overall divi-sion factor N and the comparison frequency fPFD. PLL IC manufacturerstherefore state a normalized phase noise figure which does not depend onN nor fPFD. With the relation
the actual phase noise power spectral density can be obtained. When viewedtogether with Equation (2.1), the above relation instantly reflects the im-proved phase noise performance (i.e. lower phase noise) for the same outputfrequency but higher comparison frequency, as the decreased division factorN has more impact than the increased comparison frequency fPFD.
The ADF4153 has the lowest phase noise, which is the most importantfigure in this overview.
Spurious Lines (Spurs): These unintended spectral lines degrade the outputsignal in dependence on the frequency difference from the center frequency(for example 100 kHz). They should be as low as possible, and the mostpromising PLL IC in this context is the ADF4153.
Modulus Range: Recalling (2.3), the modulus F should be high to providesmall frequency steps. The modulus is key to achieve a step size in therange of 1 kHz while employing a 10 MHz reference oscillator, regardlessof the division factor R before the phase-frequency detector. All shownPLL IC models feature at least a 12-bit modulus, which is adequate. TheNational models moreover allow for a 22-bit modulus.
Number of Charge Pump Current Levels: Different current plateaus at thephase-frequency detector’s output are an advantage, since the loop param-eters for a specific output can be altered without changing the hardware,most of all the loop filter. When aiming for best phase noise performance,small charge pump currents are preferred, since the effect is similar to fur-ther increased capacitor values (which are already large) in the loop filter.With the exception of the ADF4252, all models compared here have 16programmable charge pump current levels.
The presented parameters are an assortment to discuss some important issues forthe practice. For thorough part descriptions, please refer to the data sheets [4],[7], [8] and [9].
20
2.3 Loop Filter Design
After careful consideration I have chosen the ADF4153 PLL IC for both syn-thesizers described in this diploma thesis.
Specifications
This section emphasizes important specifications of the ADF4153 PLL IC tosummarize in more detail than Table 2.1. All data is provided by [4].
Parameter Conditions, CommentsRF input frequency 0, 5 ÷ 4, 0 GHz −8 dBm min / 0 dBm maxfref input frequency 10 ÷ 250 MHz slew rate > 25V/µsfref input sensitivity 0, 7 ÷ AUDD V peak-peak; AUDD: supplyfPFD,max 32 MHzCharge pump current
High plateau 5 mA typLow plateau 312, 5 µA typ
Power suppliesAUDD 2, 7 ÷ 3, 3 VUP AUDD ÷ 5, 5 VIDD 24 mA max
Table 2.2: ADF4153 Fractional-N PLL IC Specifications.
2.3 Loop Filter Design
The loop filter impedance Z(s) for the passive second order loop filter shown inFigure 2.4 is given by:
Z(s) =
(
R2 + 1
sC2
)
1
sC1
R2 + 1
sC1
+ 1
sC2
=1 + sR2C2
s2R2C1C2 + s (C1 + C2)(2.11)
With the definitions
T1 , R2 ·C1C2
C1 + C2
(2.12)
T2 , R2C2 (2.13)
Ctot , C1 + C2 (2.14)
expression (2.11) can be written as
Z(s) =1 + sT2
sCtot (1 + sT1)(2.15)
21
2.3 Loop Filter Design
1C
To VCOFrom Charge Pump
2C
2R
)(sZ
Figure 2.4: Topology of the Passive Second Order Loop Filter.
)(sZ
H
Loop Filter VCO
Frequency Divider
Phase Detector
K sKVCO
/
reffoutf
Figure 2.5: The Phase-Locked Loop System.
From Figure 2.5 we gather the open loop gain G(s):
G(s) =Kφ · KV CO
s· Z(s) (2.16)
In the formula above, KV CO is the tuning sensitivity of the VCO, which givesthe frequency change of the VCO output caused by a specific tuning voltagechange. Kφ characterizes the phase detector and involves the charge pump cur-rent. The system function for the VCO is KV CO
s, as it serves as integrator with
respect to the output phase. All in-band noise sources of the PLL configuration,such as the phase detector noise, the R divider noise, the N divider noise and thereference oscillator noise have the common factor
G(s)
1 + G(s)H
in their respective transfer functions, where we identify H ≡ 1
N. Note that H
does not depend on s. Two important parameters of the phase-locked loop, the
22
2.3 Loop Filter Design
loop bandwidth ωc and the phase margin φ, can now be defined.
In order to maximize the phase margin at the loop bandwidth angular frequencywe use the approach
dφ
dω
ω=ωc
!= 0 (2.20)
The immediate outcome is
ωcT2 =1
ωcT1
(2.21)
and thus T2 can be expressed by T1 and ωc. Substituting 1
ωcT1
for ωcT2 in Equation
(2.19) produces10
φ − π = arctan
[
1
2
(
1
ωcT1
− ωcT1
)]
or, equally,
tanφ =1
2
(
1
ωcT1
− ωcT1
)
. (2.22)
Now T1 can be explicitly expressed by solving (2.22). This allows to subsequentlyderive T2 and further Ctot. The time constants T1 and T2 depend on the phasemargin φ and the loop bandwidth ωc only, while the sum capacitance Ctot alsodepends on the phase detector, the VCO and the frequency divider.
T1 =1
ωc
[
1
cos φ− tan φ
]
(2.23)
T2 =1
ωc2T1
(2.24)
Ctot =Kφ · KV CO
N · ωc2
·
[
1 + ωc2T2
2
1 + ωc2T1
2
]1/2
(2.25)
Recalling the definitions (2.12)–(2.14), this set of expressions finally leads tothe loop filter part values as used on the PCB:
C1 = Ctot ·T1
T2
(2.26)
10arctanx + arctan y = arctan(
x+y
1−xy
)
23
2.3 Loop Filter Design
C2 = Ctot − C1 (2.27)
R2 =T2
C2
(2.28)
The part values C1, C2 and R2 of the passive second order loop filter can thusbe derived in close form.
Choosing Phase Margin and Loop Bandwidth
In the calculation above, the phase margin φ and the loop bandwidth ωc mustbe chosen. The phase margin φ relates to the transient response of the PLL ata frequency change. Sufficient phase margin is required for closed loop stability.The higher φ, the better transient ringing is dampened. Typical phase marginsdesign targets range from φ = 40 ÷ 50.
Choosing the loop bandwidth ωc is finding an optimum between two goals:
1. Minimizing RMS11 phase errors and the
2. suppression of spurious lines.
To minimize RMS phase errors, ωc is chosen so that the PLL noise equals theVCO noise. On the other hand, improved rejection of spurs and noise requiresnarrow loop bandwidth.
For the given requirements using a second order passive loop filter, one shouldopt for designing the loop filter to achieve narrow ωc, thus emphasizing the secondgoal. Observing the formulas above, this approach means
- small Kφ (through small charge pump current setting) and
- large capacitor values in the loop filter.
Available capacitors naturally limit the maximum aspired capacitance values.High quality film types take up much more physical space than their low perfor-mance counterparts. Regrettably, the most desirable components for this appli-cation also take up the most physical space, are very expensive and often are notavailable in SMD12 packages.
11Root Mean Square12Surface Mounted Device
24
Chapter 3
The Phase-Locked LoopSynthesizer for 1087,5 MHz
In this chapter the first local oscillator (LO1) will be depicted from a descriptionof each chosen component to the part arrangement in both circuitry and on thePCB. Figure 3.1 shows a picture of the LO1 synthesizer PCB.
Figure 3.1: Picture of the LO1 1087,5 MHz Synthesizer PCB.
25
3.1 Requirements
3.1 Requirements
For the test and measurement equipment, requirements have been stated for thefirst local oscillator, summarized in Table 3.1.
Output center frequency 1087, 5 MHzOutput frequency range 1037, 5 MHz ÷ 1137, 5 MHzPhase noise power spectral density < −70 dBc/Hz for |∆f | = 10 kHz
< −85 dBc/Hz for |∆f | = 25 kHzSpurious lines < −50 dBc for |∆f | < 50 kHzFrequency step size < 10 kHzCircuit board material FR4 1,6 mmReference frequency 10 MHzReference feed internal or externalFrequency control µC typeMain supply voltage 12 V DCPhysical dimensions
Length 160 mm max.Width 80 mm max.Height 14 mm max.
Table 3.1: LO1 Requirements.
To meet the demands concerning phase noise and spurious lines of the outputspectrum, a high performance synthesizer is required. This is of particular im-portance in the context of frequency conversion with mixers. A frequency controlusing the MSP430F149 microcontroller is covered in Chapter 5. Because manyincorporated RF components are powered by voltages other than 12V DC, a sep-arate voltage regulator PCB with four additional voltage outputs is presented inSection A.3. For the choice of the OCXO, the height limit of only 14 mm was anadditional challenge. Furthermore, SMB connectors are used to save space.
26
3.2 Components
3.2 Components
The phase-locked loop assembly consists of several components arranged on onePCB as shown in Figure 3.2.
Mercury
OC14T5A
OCXO
Crystek
CVCO55BE
0960-1200
RF OUT
REF IN
REF OUT
Mini Circuits
MAV-11SM
Jumper
Analog Devices
ADF4153BRU
Burr-Brown
BUF634
Power Divider
Loop Filter
Figure 3.2: PCB Overview of the 1087,5 MHz Synthesizer.
In the following, the depicted components will be addressed.
3.2.1 Reference Oscillator
As 10 MHz reference oscillator I have chosen a crystal oscillator with an oven con-trol to stabilize the unit’s temperature. All high performance oscillators profitfrom stabilized working conditions like the oven control, as the output frequencydrifts with the crystal temperature in most other circumstances. Oven controlcombined with a massive metal package makes the oscillator unit almost unaf-fected from environmental temperature fluctuations (given moderate environmenttemperatures). The type of crystal cut refers to the crystal symmetry plane andinfluences the stability attributes. Table 3.2 is an extract from [10].
27
3.2 Components
Frequency 10 MHzType of crystal cut AT
Initial frequency accuracy < ± 2 ppm (± 20 Hz)Frequency stability versus
Temperature (0 C to +60 C) ± 0, 2 ppm typ.Long term aging < ± 0, 7 ppm first year
Output wave form HCMOS square waveLogic high 4, 5 V min.Logic low 0, 4 V max.Duty cycle 40% to 60%Electronic frequency control
Frequency deviation range ±4 ppm min.Control voltage range 0, 0 V to 5, 0 VInput impedance > 47 kΩ
Supply voltage 5, 0 VCurrent draw < 260 mA at turn-on
Table 3.2: Mercury OC14T5A OCXO Specifications.
Table 2.2 shows that the slew rate of the reference input signal is critical. Infact the input is triggered by observing the zero crossings of the reference signal.It is obvious that the HCMOS square wave provided by the OCXO is the preferredsignal for this purpose. When using less steep zero crossing transitions, accuratetriggering becomes more difficult and is prone to timing errors known as jitter,translating into output spectrum noise. The noise is caused by the statisticalnature of the jitter timing errors.
An additional feature is the electronic frequency control (EFC) input thatallows to ”pull” the oscillator frequency fref by applying a DC control voltage atthe EFC pin. This allows to change the output frequency by ±4 ppm (±40 Hz).Reviewing (2.9), the synthesizer output frequency fout is directly proportional tofref . When required, the synthesizer output can be set to an arbitrary centerfrequency within the possible range by fine-tuning fref with EFC.
The LO synthesizer implementation in this diploma thesis leaves the EFCvoltage constant for best noise performance. Moreover, the 12-bit modulus of theADF4153 PLL IC is utilized to produce a frequency step size which is alreadybetter than stated in the requirements.
28
3.2 Components
3.2.2 Burr-Brown BUF634 Buffer Amplifier
This amplifier is used as a DC-coupled impedance buffer for the 10 MHz referenceoscillator. The buffer with low output impedance is capable of delivering currentsup to ±250 mA, which certainly allows to trigger the ADF4153 PLL IC referenceinput and at the same time drive a 10 MHz output.
A jumper selects the buffer input, which can be either
- the on-board reference oscillator or
- an external oscillator via input jack.
The buffered reference signal is led to the PLL IC and the 10 MHz output. Thisfeature allows to configure the synthesizer PCB either as ”master” or ”slave”regarding the reference oscillator, which permits different scenarios:
- All LOs use the on-board 10 MHz oscillator, i.e. all LOs are configured as”master”.
- The master LO will provide the reference signal for all other slave LOs.Thus all synthesizer units are in sync because of the mutual reference clock.A slave unit is able to pass the buffered master clock on to the next slaveunit.
- All LOs can also be used in conjunction with one auxiliary external clock,meaning that all units are operating in ”slave” mode.
Specifications
The BUF634 data sheet [11] describes two modes of operation, a low quiescentcurrent mode and a wide bandwidth mode that works with ten times the biascurrent. Of course, the wide bandwidth mode is utilized to use the BUF634 withits full potential.
The amplifier was chosen for its uncompromised large signal bandwidth com-bined with high output current capability, whereas other products have widebandwidth only for small signal operation. This is important, because the ref-erence oscillator signal is a square wave with peak-to-peak value of up to 5V,cf. Table 3.2. Voltage gain is not intended; the amplifier serves as impedancebuffer only. The device is operated with ±12 V on the synthesizer PCB.
3.2.3 Crystek 960-1200 MHz VCO
The VCO pad connections are straightforward: There is the tuning voltage input,the RF output (50Ω), and the Ucc pad for the supply voltage. All other padsconnect to ground.
The VCO tuning voltage requirements are well met by the Analog Devices ADF4153PLL IC, which supports a supply voltage of up to 5, 5 V for the charge pumpoutput. This allows to use the preferred passive loop filter instead of an activefilter.
As the tuning curve, which shows output frequency versus tuning voltage, isnot linear [12], the typical tuning sensitivity is stated. The tuning sensitivity isan important phase-locked loop parameter.
Input Capacitance
The VCO input capacitance naturally influences the loop filter impedance. Aslong as a second order passive loop filter is used, the loop filter components usuallyinclude relatively large capacitors. In comparison, the VCO input capacitance of30 pF is relatively small and can be neglected. Section 3.2.6 will verify that theloop filter capacitances exceed 30 pF by more than three orders of magnitude forthis presented synthesizer. This does not hold true for some passive loop filters
30
3.2 Components
of higher order. The VCO input capacitance then becomes relevant.
3.2.4 Mini Circuits MAV-11SM Amplifier
The main task of this component is to provide isolation between the synthesizeroutput and the VCO, thus reducing interference caused by unstable load condi-tions. The according isolation from amplifier port 2 (amplifier output) to port 1(amplifier input) is expressed by the scattering parameter S12. In the forwarddirection on the other hand, power gain is provided, expressed by S21.
Of primary interest is the behavior of the MAV-11SM first for frequenciesin the range 1087, 5 MHz± 50 MHz. Table 3.5 is an excerpt of the data sheetfrom Mini Circuits, where we gather through interpolation |S12| ≈ −14 dB and|S21| ≈ 10 dB for the center frequency 1087, 5 MHz.
Next, we observe |S21| for the 2nd harmonic at 2175 MHz, where |S21| ≈ 7 dB.Together with the VCO second harmonic suppression of typically 10 dBc, theexpected second harmonic attenuation at port 2 of the amplifier is therefore13 dBc (the fundamental frequency experiences 3 dB more gain than the secondharmonic). In the complete LO system with eight outputs, a passband filter willattenuate the harmonics further. These hardware additions are beyond the scopeof this diploma thesis.
Biasing
For biasing the amplifier, an RFC1 and a DC blocking capacitor separate thequiescent current from the RF signal path. A device voltage Ud = 5, 5 V anda bias current I0 = 60 mA are suggested [13]. Given the supply voltage ofUcc = 12 V, the required resistor RBias can be specified [14]:
RBias =Ucc − Ud
I0
=12 V − 5, 5 V
60 mA= 108, 3 Ω
The RFC has high conductance at DC and can be omitted in the calculation
1Radio Frequency Coil (Choke): An element that acts as inductance up to its resonancefrequency in a RF circuit.
31
3.2 Components
MAV-11SM
4
1 3
2
BiasR
L (RFC)
Input Output
I0
1,blockC 2,blockC
ccU
dU
Figure 3.3: Biasing the MAV-11SM Amplifier.
above. The power dissipation in RBias of 0,4W is handled by connecting threeresistors in parallel instead of using a single device to ensure safe part tempera-tures.
The application note [14] recommends to use an RFC that has about tentimes the impedance of the load at the lowest frequency of operation, which is1037, 5 MHz. Because of the 50 Ω system implying a 50 Ω load, the coil impedanceZL at this frequency should be about 500 Ω. On the other hand the series reso-nance frequency fres of the RFC must be above the maximum operation frequencyof 1137, 5 MHz. It requires a specialized RFC to have both enough inductance(to isolate the biasing circuitry from RF) and high fres.
For building the circuit, a 68 nH coil with fres = 1200 MHz is used, whichhas ZL = 443 Ω at 1037, 5 MHz. DC-blocking capacitors with Cblock,i = 22 pFare chosen. They have a series resonant frequency just above the highest signalfrequency and are provided in an SMD 0805 package.
3.2.5 Analog Devices ADF4153 PLL IC
The PLL IC requires few external components for operation, mainly decouplingcapacitors are placed near the device. Specific device inputs are emphasizedbelow.
Charge Pump Setting: The resistor Rset sets the maximum charge pump cur-rent. The used default value of Rset = 5, 1 kΩ gives a 5 mA current limit.Importantly, the actual charge pump currents only match the specificationsin [4] if Rset = 5, 1 kΩ.
Complementary RF Input: ”RF IN B” is the complementary input to the RFprescaler. For the intended single-ended operation, it is decoupled to ground
32
3.2 Components
with a 100 pF capacitor.
Charge Pump Power Supply: The PLL IC offers the possibility to use ahigher supply voltage for the charge pump section. Other than the usual3, 0 V voltage limit, this circuitry can be powered by up to 5, 5 V and thuscan provide higher tuning voltages for the VCO. Combined with this fea-ture, a passive loop filter with all its advantages is therefore sufficient todrive the used VCO.
Clock, Data and Latch Enable Inputs: These are the serial inputs of the3-wire interface (CLK, DATA, LE). Each input is equipped with a series330Ω resistor, as suggested in the tech note [6].
3.2.6 Loop Filter
The values of the loop filter components are now calculated for the present1087,5 MHz synthesizer using the method explained in Section 2.3.
The loop filter has the topology shown in Figure 2.4, consisting of capacitorsC1 and C2 as well as resistor R2. This passive second order configuration waschosen because of its simplicity.
The reference oscillator’s output fref is frequency-doubled and used as com-parison frequency fPFD:
fPFD = fref ·D
R= 20 MHz,
where D = 2 and R = 1. For fout = 1087, 5 MHz this means for the divide ratiorealized by the PLL IC:
Ntot =fout
fPFD · V= 54, 375.
Because no external prescaler is used, V = 1 here. Using the reference frequencydoubler yields a 3 dB phase noise advantage over the solution with fPFD=10MHzand Ntot=108,75.
The constant Kφ is chosen to the smallest possible value realized by theADF4153 PLL IC with Rset = 5, 1 kΩ, which is Kφ = 313 µA · rad−1 to min-imize the necessary capacitances in the loop filter. If Rset = 5, 1 kΩ, the tableprovided in the datasheet[4], which describes the mapping of the charge pumpprogramming to Kφ, can be used. Rset is realized by R1 in the circuit shown inFigure 3.5.
Starting with the design values φ = 45 for the phase margin, and a loopbandwidth of 10 kHz (ωc = 2π · 10 kHz) results in
T1 =1
ωc
[
1
cos φ− tan φ
]
=1
2π · 104 s−1
[
1
cos(
π4
) − tan(π
4
)
]
= 6, 592 · 10−6 s ,
33
3.2 Components
T2 =1
ωc2T1
= 38, 42 · 10−6 s , and
Ctot =Kφ KV CO
Ntot ωc2
[
1 + ωc2T2
2
1 + ωc2T1
2
]1/2
=313 µA · 150 MHz/V
54, 375 · (2π · 104 s−1)2·
[
1 + ωc2T2
2
1 + ωc2T1
2
]1/2
= 528, 0 · 10−9As
V= 528, 0 · 10−9 F.
Ctot denotes the sum capacitance of C1 and C2 in the loop filter. The resultalready hints the substantial capacitor values, given the quality requirementsand the limited space realization with SMD components.
Finally, the loop filter component values are (referring to Figure 2.4):
C1 = Ctot ·T1
T2
= 91 nF
C2 = Ctot − C1 = 437 nF
R2 =T2
C2
= 88 Ω
The interdependence of the part values forbids to simply raise capacitor valuesto get smaller loop bandwidth, because this also alters the phase margin, at therisk of potential closed loop instability. It is recommended to check the resultingnew loop parameters for altered part values. In this case, the chosen values are:
C1 , 100 nF
C2 , 440 nF = 2 · 220 nF
R2 , 90 Ω
These are standard part values (for C2, two parallel capacitors are used). Usingfewer parts and soldering joints reduces complexity. Importantly, all capacitorsare film type of high Q-factor. The indices above comply with Figure 2.4. Forthe part indices used in the actual circuit refer to Section 3.3.
Verification for the actually used parts reveal slightly different values fromφ = 45 and ωc = 2π · 10 kHz:
φ = 43, 4
ωc = 2π · 9, 9 kHz
The frequency step size depends on the modulus F , which is set to the supportedmaximum of the PLL IC, F = 4095, so that the step size is minimal. The divisionfactor Ntot is set
Ntot = N +K
F= 54 +
K
4095
!= 54, 375
and determines the output frequency. Obviously, N is the integer part of thefractional division factor, resulting in N = 54. The above relation gives K = 1536,because only integer fractions K are supported by the PLL IC. The actual mean
34
3.3 Schematics and Layout
division factor and calculated output frequency are
Ntot = 54,37509158 ,
f0 = 1087,501832 MHz
if fref = 10 MHz and thus fPFD = 20 MHz. With this precondition, the step sizeof the synthesizer is
fstep =fref
F·DV
R=
10 MHz · 2
4095≈ 4, 884 kHz
with D = 2, V = 1 and R = 1.
3.3 Schematics and Layout
The layout for the complete circuit of the 1087,5 MHz synthesizer is designedto fit on one PCB. The board is made of low-cost FR4 material2 with copperplating on both sides. However, the relative permittivity εr may strongly varybetween board samples. As a result, the proper RF strip line width for 50 Ω linesvaries between samples. In practice, FR4 is preferably used in designs with upto 3 GHz.
One copper layer serves as a ground plane, and all ground connections fromthe top plane are realized with vias. Especially for the RF section, multiple viasare used for one ground connection to decrease inductance and resistance.
For the center frequency of 1087,5 MHz and the properties of the FR4 board(Table 3.6), a width of w = 2, 9 mm is used for a 50 Ω microstripline. Near theIC packages, tapered lines are used because of the small pin distances. All RFmicrostrip lines are made as short as possible.
Parameter ValueRelative permittivity εr 4,4÷ 4,7Substrate thickness h 1,6 mmDielectric loss, tan δ 0,014Copper plating thickness 35 µmCopper resistivity 1, 673 µΩ cm50 Ω microstrip line width w for 1,0875 GHz 2,9 mm
Table 3.6: Properties of the FR4 Circuit Board.
Figure 3.5 shows the schematics of the LO1 synthesizer PCB. The center ofthe circuit is the ADF4153 PLL IC that gets an equivalent of the RF outputsignal, which is then scaled down by the PLL IC by performing a frequencydivision with a factor of Ntot. The result is compared to the reference signal with
2Flame Resistant 4
35
3.3 Schematics and Layout
fundamental fref . According to the register programming, a charge pump (CP)output is created.
This output current is filtered by the loop filter R6 and C18, C19, C20 andpassed on to the VCO tuning input (VT). Based on the tuning voltage, the VCOgenerates an RF output. 50 Ω microstrip lines are used for transmission of theRF signal.
A 6 dB power divider consisting of the resistors R2, R3, R4 with ≈ 50
3Ω
directs 1
4of the VCO output power towards the output amplifier and 1
4towards
the PLL IC for comparison with the reference. The rest of the VCO outputpower is dissipated within the resistors. This 3-port power divider is matched to50 Ω at every port. The DC blocking capacitors C10, C11, C12 (22 pF) are usedthroughout.
The output amplifier MAV-11SM, which is biased by L5, R14, R15 and R16,provides gain and isolates the RF section from the load at the RF output RF OUT.This output is DC-blocked by C13.
Inputs CLK, DATA and LE form the 3-wire interface for frequency control com-munications with the microcontroller (Table 5.2).
Reference oscillator OCXO OC14T5A generates a HCMOS compatible squarewave signal with fundamental fref = 10 MHz. This signal or an external signalREF IN, depending on the setting of the jumper, is transferred to the a high-current, high-bandwidth buffer amplifier BUF634P. From there, it is brought toboth the reference input of the PLL IC and the SMB type REF OUT connector onthe PCB.
The supply voltages are provided by a separate PCB with voltage regulatorsthat is presented in Section A.3.
36
3.3 Schematics and Layout
Figure 3.4: Top Layer Layout of the 1087,5 MHz Synthesizer PCB.
37
3.3 Schematics and Layout
V+
RF OUT
CVCO55BE-
0960-1200U2
C5
L5
R14
3 1
2
4
C13 C12 R4 R3
R2
R5
C10
C9 R1
R6
C18
C19
C20
C16
C14 C15
C17
L4C11
C1
C2
C3
C4 C6
C7 C8R7 R8 R9
L1
C23C21
L2
C22
C24
C26
C27
+
+
C29 C25
R13
R12
R11
R10
C28
R15 R16
22 pF 22 pF 18 18
18
50
22 pF
100 pF
22 pF
332 332 332
10 pF
10 pF
10 pF 10 pF
10 pF
100 nF
100 nF 100 nF 100 nF
330 330 330
10 nF 1
100 nF10 pF
100
220 nF
220 nF
100 nF
90
5,1 k
100
1 10
1
10
100
110 pF
470
470
10
10
220
220
68 nH
U1
ADF4153BRU
U3BUF634P
U4OC14T5A-10.000
U5
MAV-11SM
3 V
SUPPLY
12 V
SUPPLY
-12 V
SUPPLY
5 V
SUPPLY
CLKDATA
LE
REF
OUT
REF
IN
H
H
H
F
FF
F
F
F
F
F
Vo
Vin V-BW
8
7 1
14
67
1 3 4
9 10 11 12 13 15 16
12345678
REFIN AVDD RFINA RFINB AGND CPGND CP RSET
DGND SDVDD CLK DATA LE DVDD VP
RF VCC
VT
* RF STRIP LINE 50
* * * *
** RF T-JUNCTION 50
**
**
+
+
+
+
+
+
4,4 V
SUPPLY
Figure 3.5: Schematic of the 1087,5 MHz Synthesizer PCB.
38
Chapter 4
The Phase-Locked LoopSynthesizer for 4252,5 MHz
The second local oscillator (LO2) is a synthesizer with f0 = 4252, 5 MHz, whichreutilizes some of the circuit technology from the synthesizer board described inChapter 3. The whole RF section is newly designed, introducing an externalprescaler frequency divider and an improved circuit board material to meet therequirements of the higher center frequency. In addition, an according loop filterdesign is presented. Figure 4.1 shows a picture of the LO2 synthesizer PCB.
Figure 4.1: Picture of the LO2 4252,5 MHz Synthesizer PCB.
39
4.1 Requirements
4.1 Requirements
Table 4.1 summarizes the requirements for the LO2 synthesizer:
Output center frequency 4252,5 MHzOutput frequency range 4227, 5 MHz ÷ 4277, 5 MHzPhase noise power spectral density < −70 dBc/Hz for |∆f | = 10 kHz
< −85 dBc/Hz for |∆f | = 25 kHzSpurious lines < −50 dBc for |∆f | < 50 kHzFrequency step size < 10 kHzCircuit board material Rogers RO4003C 0.032”Reference frequency 10 MHzReference feed internal or externalFrequency control µC typeMain supply voltage 12 V DCPhysical dimensions
Length 160 mm max.Width 80 mm max.Height 14 mm max.
Table 4.1: LO2 Requirements.
4.2 Components
This section introduces the parts the synthesizer is built of. Some parts werealready discussed in detail in the previous chapter and are only listed here.
4.2.1 Overview
Some areas of the synthesizer circuit technology do not depend on the output fre-quency and are reutilized from the 1087,5 MHz synthesizer design from Chapter 3.The following Figure 4.2 emphasizes the main components on the LO2 PCB,which are discussed in the subsequent sections.
40
4.2 Components
Mercury
OC14T5A
OCXO
Crystek
CVCO55BH
4100-4300
REF IN
Jumper
RF OUT
REF OUTAnalog Devices ADF4153BRU
Burr-Brown
BUF634
Power DividerLoop Filter
Hittite HMC432
Agilent
MGA-82563
Figure 4.2: PCB Overview of the 4252,5 MHz Synthesizer.
These parts from LO1 are identical for the LO2 synthesizer:
- The 10 MHz reference oscillator (Section 3.2.1),
- the BUF634 buffer amplifier (Section 3.2.2), and
- the ADF4153 PLL IC (Section 3.2.5).
However, the PLL IC now requires an external prescaler (Section 4.2.3), becausef0 = 4252, 5 MHz exceeds the RF input specification of 4000 MHz. Furthermore,evidently a new loop filter setup and frequency programming are necessary (Sec-tion 4.2.5).
4.2.2 Crystek 4100-4300 MHz VCO
For the LO2 center frequency f0 = 4252, 5 MHz, a different voltage-controlledoscillator[15] is used. Its characteristics are shown in Table 4.2:
41
4.2 Components
Parameter SpecificationOutput frequency 4100 MHz ÷ 4300 MHzOutput power 2 dBm ÷ 6 dBmPhase noise power spectral density
1 kHz offset −47 dBc/Hz10 kHz offset −90 dBc/Hz
100 kHz offset −113 dBc/HzHarmonic suppression (2nd harmonic) 15 dBcTuning voltage 0,5 V ÷ 4,5 VTuning sensitivity KV CO 100 MHz/VInput capacitance 10 pFLoad impedance 50 ΩSupply voltage 5,0 V
Here the required tuning voltage at the VT port is Utun ≈ 3, 6 V for 4252,5 MHzand Utun ≈ 4, 1 V for the required maximum of 4277,5 MHz. The VCO thereforemakes use of the independent charge pump supply voltage UP of the ADF4153PLL IC (cf. Table 2.2). This circuit section is operated with UP = 4, 4 V toguarantee the required frequency range, while the rest of the PLL IC device usesonly 3 V.
Like the VCO for LO1, the Crystek CVCO55BH-4100-4300 has pads for groundconnections, the supply voltage, the tuning voltage and the RF output.
4.2.3 Hittite HMC432 Prescaler
For the 4252, 5 MHz synthesizer a separate frequency divider (prescaler) is nec-essary in the return path to the PLL phase frequency detector. That is becausethe maximum allowed input frequency of the ADF4153’s frequency divider isonly 4, 0 GHz (cf. Table 2.2). Through the HMC432 divide-by-2 prescaler, theADF4153 receives 1
2· 4, 252 GHz = 2, 126 GHz at the RF input.
The Hittite HMC432 (cf. Table 4.3) features ”ultra low” SSB1 additive phasenoise, operation up to 8 GHz at the input, and single-ended ports[16]. Through-out the synthesizer the signal path is single-ended. According ports on theHMC432 help to keep circuit complexity low and signal quality unimpeded, be-cause conversion between single-ended and balanced signals (with a balun2 is notrequired.
Both the RF input and output require DC blocking because of their circuittopology. The DC blocking capacitors are chosen to have series resonance (lowimpedance) just above the maximum intended operation frequency.
1Single Sideband2Balanced–Unbalanced Converter
42
4.2 Components
Parameter SpecificationInput frequency 0, 2 ÷ 8 GHzOutput power (fin = 4 GHz) −6 dBm ÷ −3 dBmInput power range (fin = 1 ÷ 7 GHz) −12 dBm ÷ 12 dBmSSB phase noise power spectral density
100 kHz offset −148 dBc/HzReverse leakage (RF output terminated, fin = 4 GHz) −30 dBmSupply voltage 3,0 VSupply current draw 42 mA
The task of this amplifier is to provide gain to the RF signal and to improveisolation between the synthesizer RF output port and the VCO by attenuatingwaves reflected towards the VCO.
Parameter SpecificationInput frequency 0, 1 ÷ 6 GHzGain (at 4 GHz) 10, 7 dBOutput power at 1 dB gain compression P1dB +17, 0 dBmOutput third order intercept point +31, 0 dBmNoise figure 2, 9 dB max.Input VSWR 1, 8 : 1Output VSWR 1, 2 : 1Supply voltage 3,0 VSupply current draw 84 mA
This GaAs PHEMT3 amplifier has beneficial attributes like unconditional sta-bility, good matching at the input and output ports to a 50 Ω system and high1 dB compression point P1dB. Table 4.4 gives a quick overview of the specifica-tions, while typical scattering parameters according to [17] are shown in Table 4.5.Port 1 is the amplifier input, port 2 is the output.
At the operation frequency f0 = 4252, 5 MHz, |S12| = −20 dB, which con-tributes to the isolation of the load at port 2 from the PLL at port 1. At thesame time the device features |S21| ≈ 10, 4 dB gain in the forward direction atf0.
As seen in the schematics (Figure 4.4) the MGA-82563 is biased by a RFCwith L = 22 nH at the output (pin 6) like suggested in the data sheet[17]. DC
blocking capacitors in 0603 SMD packages with 1, 8 pF are present at the amplifierinput and output. The DC block also has low impedance at the operationalfrequency f0 = 4252, 5 MHz, and the capacitor is therefore chosen to have itsseries resonance slightly above the highest frequency of operation (also see thepart list A.2).
4.2.5 Loop Filter
This synthesizer has a second order passive loop filter like shown in Figure 2.4.All filter component values are calculated in this section.
To boost phase noise performance by 3 dB, the frequency doubler feature ofthe PLL IC is engaged (D = 2, R = 1) to obtain
fPFD = fref ·D
R= 20 MHz.
As a consequence of the maximum rated input frequency of 4 GHz at the PLL IC’sRF input, an external frequency prescaler V = 2 is introduced. The VCO outputfrequency fout = 4252, 5 MHz therefore produces an 2126, 25 MHz input at thePLL IC. With the following, the divider factor equation can be solved for thefraction K. The fact that only integer values of K are possible must be regarded.
fout = fPFD · Ntot · V = 20 MHz ·
(
N +K
F
)
· 2
= 20 MHz ·
(
106 +K
4095
)
· 2!= 4252, 5 MHz
For minimum frequency step size, the modulus F is programmed to the supportedmaximum of F = 4095. N is the integer part of the division factor: in this case,N = ⌊4252,5
2·20⌋ = 106. This means for the fraction: K = 1280. With these settings,
the actual mean division factor Ntot and center frequency f0 will be
Ntot ≈ 106, 312576
44
4.3 Schematics and Layout
f0 ≈ 4252, 503052 MHz
at a frequency step size of
fstep =fref
F·DV
R=
10 MHz · 4
4095≈ 9, 768 kHz
if fref = 10 MHz. Because of the divide-by-2 prescaler, an actual frequencychange of ∆f at the VCO causes a frequency change of ∆f
2at the PLL IC input.
This results in the equivalent tuning sensitivity
K ′
V CO =KV CO
V= 50 MHz/V.
For calculating the loop filter component values, also the loop bandwidth ωc andthe phase margin φ are required. I have chosen a loop bandwidth of 10 kHz(ωc = 2π · 104 s−1) and a phase margin φ = 50 for minimum RMS phase errors.The phase detector constant Kφ was programmed to 2, 5 mA·rad−1. With calcu-lated T1, T2 and Ctot by means of Equations (2.23)–(2.25) the chosen parts are(2.26)–(2.28):
C1 , 100 nF,
C2 , 660 nF = 3 · 220 nF,
R2 , 63 Ω.
This results in a loop bandwidth of 10,3 kHz and a phase margin φ = 50, 1. Inthe schematic depicted in Figure 4.4, the loop filter consists of the parts R13, C25,C26, C27 and C28.
4.3 Schematics and Layout
In Figure 4.4, the schematics are depicted. The layout for the circuit board(cf. Table 4.6) was created with the components and transmission lines on thetop side of the PCB. A ground plane is present on the bottom side of the circuitboard. Vias are used for establishing contact to circuit ground. Especially in theRF section, multiple vias are required for proper connection to ground (resultingin reduced via inductance and resistance).
The RF output of the synthesizer is generated by the VCO, CVCO55BH.The DC-blocking capacitor C17 is placed between the VCO and the 6 dB powerdivider consisting of R7, R8 and R9, ≈ 50
3Ω each. The outputs of the power
divider lead to the RF output amplifier MGA-82563 and the HMC432 divide-by-2prescaler, which forms the return path to the RF input of the PLL IC, RFINA. TheDC-blocking capacitors C15, C16, C17, C18 are chosen to have series resonance justabove the maximum synthesizer frequency f0,max = 4, 2775 GHz. Transmissionlines in the RF section are 50 Ω microstrip lines with a width w =1,8mm. Near
45
4.3 Schematics and Layout
the device input pins, the microstrip lines are tapered where required to meet theactual pin pitch requirements.
The PLL IC receives the HCMOS reference signal with fundamental frequencyfref = 10 MHz at the REFIN input. It is compared to the divided RF output ofthe divide-by-2 frequency prescaler HMC432 coming to the PLL IC at the single-ended RF port RFINA. After the frequency conversion, the DC-blocking capacitorsC10 and C11 have series resonance slightly above
f0,max
2= 2138, 75 MHz for best
signal transmission. The prescaler output is terminated by R12 = 50 Ω.
Parameter ValueRelative permittivity εr 3, 38 ± 0, 05Substrate thickness h 0,813 mmDielectric loss, tan δ 0,0024Copper plating thickness 35 µmCopper resistivity 1, 673 µΩ cm50 Ω microstrip line width w 1,8 mm
Table 4.6: Properties of the RO4003C 0.032” Circuit Board Material.
The comparison performed by the phase-frequency detector yields a currentsource (”charge pump”) output at pin CP. By passing the loop filter consisting ofR13, C25, C26, C27 and C28, the charge pump output generates the tuning voltagefor the VT frequency control input of the VCO.
Depending on the jumper setting, either the HCMOS square wave output ofthe internal reference oscillator OC14T5A with fundamental fref = 10 MHz, oran external reference connected to the REF IN input of the PCB, are passed onto the BUF634 buffer. This buffered signal is present at the reference output REFOUT connector of the PCB and also led to the REFIN input pin of the PLL IC.
The data input pins CLK, DATA and LE of the PLL IC are the 3-wire interfacefor communications with the µC for frequency controlling purposes.
Power is supplied by a specially designed DC regulator PCB, which is pre-sented in Section A.3 of the Appendix.
46
4.3 Schematics and Layout
Figure 4.3: Top Layer Layout of the 4252,5 MHz Synthesizer PCB.
47
4.3 Schematics and Layout
CVCO55BH-
4100-4300
U1
ADF4153BRU
U5
9 10 11 12 13 15 16
12345678
REFIN AVDD RFINA RFINB AGND CPGND CP RSET
DGND SDVDD CLK DATA LE DVDD VP
RF VCC
VT
* RF STRIP LINE 50
** RF T-JUNCTION 50
V+U3
BUF634P
Vo
Vin V-BW
67
1 3 4
U4OC14T5A-10.000
8
7 1
14
L2
68 H
R11
R10
470
470
C35 C36110 pF F+
C31
C32
1
10
F
F+
+
C30
C29
+
+
10
10
F
F
C34C331 10 FF
+ +
L5
100 H
C5C3
C4 C6
C7 C8
10 pF 10 pF
10 pF
100 nF 100 nF
100 nF
R1
5,1 k
R13
C25
C28
C27 220 nF
220 nF
100 nF
63
C26 220 nF
C21 C23
10 nF
100 nF10 pF
F1
+
C22 C24
R2 R3 R4
330 330 330
C1
C2
R6
R5
10 pF
100 nF
220
220
C9100 pF
C106,8 pF
R12
50
C116,8 pF
C151,8 pF
C171,8 pF
C161,8 pF
C181,8 pF
R918
R718
R818
L4100 H
C12
C13
10 nF
1 nFF1C14
+
L368 H
L1100 H
L622 nH
F1C20 +
+100 pFC19
U6
HMC432
U2MGA-82563
2
VCC
3
5 6
GNDIN
OUT
GND
2 31
5 46
GNDOUT
IN
CLKDATA
LE
REF
OUT
REF
IN
12 V
-12 V
5 V
4,4 V
3 V
RF OUT *
*
*
*
**
**
*** TAPERED RF LINE
***
***
***
***
Figure 4.4: Schematic of the 4252,5 MHz Synthesizer PCB.
48
Chapter 5
Setting Output Frequencies withthe TI Microcontroller
The synthesizer requires programming to set a desired output frequency. Allnecessary information is stored in the registers on the PLL IC. To access theseregisters, the IC has a control interface, the 3-wire interface, which gets inputdata from a low-current microcontroller from Texas Instruments1. In a bit-serialmanner, the µC sends control words of up to 24 bits length to the PLL IC. Tofinally obtain a frequency output, a set of four control words is transferred.
This chapter describes how to derive the control data words and how theyare sent to the PLL IC. I have developed a microcontroller program that handlesthe syntax and timing of the transfer. The assembler program code is shown inSection 5.3.
5.1 Generating PLL IC Register Data Sets
A data set, as described in this section, assigns custom values to all the PLL ICregisters. Thus, it is possible to set an output frequency and different modes ofoperation as well as tuning the PLL values to fit the setup. As shown in the PLLIC documentation [4], the control information is organized in four control words,which are identified by the control bits C2 and C1:
Table 5.1: Truth Table of the Control Bits C2 and C1.
1The model used is the MSP430F149
49
5.1 Generating PLL IC Register Data Sets
The registers are divided in several bit fields of different length to accommo-date all control values:
N Divider Register: This register contains two parameters that immediatelyinfluence the output frequency, namely the integer division factor N in theform of INT and the fraction K, represented by FRAC. Bit 23 (FASTLOCK) willalways set the maximum charge pump current, regardless of the CP CURRENT
setting in the control register. For this application, bit 23 is not set.
23 22 14 13 2 1 0
FA
ST
LO
CK
0 0INT FRAC
Figure 5.1: N Divider Register Map.
The value written to the N Divider Register is therefore:
N Divider Register = N · 214 + K · 22 (5.1)
R Divider Register: The R Divider scales down fref from the reference oscil-lator by the division ratio R. MOD contains the value for the modulus F .Bit 18 (PRESCALER) switches the internal prescaler of the ADF4153 between4/5 (bit not set) and 8/9 (bit set). A prescaler value 8/9 is required forPLL IC input frequencies above 2 GHz, see [4] for further information. Theunspecified bits are cleared per default.
23 22 14 13 2 1 0
0 1
20 19 18 17
LO
AD
CO
NT
RO
L
RE
SE
RV
ED
PR
E-
SC
AL
ER
MODR COUNTERMUXOUT
Figure 5.2: R Divider Register Map.
R Divider Register = PRESCALER · 218 + R · 214 + F · 22 + 1 (5.2)
Control Register: By setting bit 11, the reference frequency doubling can beenabled. If this bit is set, it has the function of D=2 with respect toEquation (2.8) ff. Bits 10 to 7 program the charge pump (current source)plateau. See [4] for the mapping bits vs current. Important is also thePD POLARITY bit, that must be set for passive loop filters if the VCO slopeof frequency vs control voltage is positive.
50
5.2 3-Wire Interface
15 2 1 0
1 0
12 11 10 9 7 6 5 4 3
RE
F.
DO
UB
LE
CP
/2
PD
PO
LA
RIT
Y
LD
P
PO
WE
R-
DO
WN
CP
3-S
TA
TE
CO
UN
TE
R
RE
SE
TCP
CURRENTRESYNC
Figure 5.3: Control Register Map.
Control Register = (D − 1) · 211 + (CP/2) · 210 +
+ (CP CURRENT) · 27 +
+ (PD POLARITY) · 26 + 2 (5.3)
Noise and Spur Register: The NOISE AND SPUR MODE bits enable built-in op-timizations for best noise performance or best spur suppression. Setting thebits 9 to 6 as well as bit 2 enables the ”Lowest Noise Mode” of the PLL IC.The opposite optimization is the ”Lowest Spur Mode”, which is selected byclearing the bits 9 to 6 and bit 2. It is also possible to set a mode with acombined approach for both noise and spur reduction.
2 1 0
1 1
10 9 6 5 3
RE
SE
RV
ED
NO
ISE
AN
D S
PU
R
MO
DENOISE AND SPUR
MODERESERVED
Figure 5.4: Noise and Spur Register Map.
To enable the ”Lowest Noise Mode”, the register value is
The ”Lowest Spur Mode” is selected by setting the register value
Noise and Spur Register = 3h.
5.2 3-Wire Interface
The ADF4153 PLL IC has a 24-bit shift register for user data input. In thissection the use of the 3-wire interface and the programming syntax of the IC isexplained.
51
5.2 3-Wire Interface
The 3-wire interface lines are
- Clock (CLK)
- Data (DATA)
- Latch Enable (LE).
Data is first transferred in serial manner into the 24-bit input shift register, eachbit being clocked in on the rising edge of CLK. The MSB2 is entered first, finishingwith the LSB3. The last to bits entered into the shift register will be interpretedas the control bits C2 and C1, whereas C1 is the LSB. Then, on the rising edgeof LE, data is transferred into the destination control register determined by thecontrol bits, cf. Table 5.1. To load the full register data set, four consecutive datawords are transferred. Figure 5.5 shows the timing constraints of the ADF4153
6t
Bit 3
1t
t
t
t
Bit 2 Bit 1 Bit 0 (LSB) Bit 23 (MSB) Bit 22
Data Word i+1Data Word i
Voltage
0 V
3 V
0 V
3 V
Voltage
0 V
3 V
VoltageCLK
DATA
LE
1t
6t
… LE Setup Time
… CLK to LE Setup Time
Figure 5.5: ADF4153 3-Wire Interface Timings.
3-wire interface. The transfer data rate is not critical, because the time from afrequency change initiation to PLL lock is not critical in this application. Sometiming parameters must be considered also for low data rate transmission. Theminimum recommended LE setup time and the CLK to LE setup time from [4]must be regarded.
It must be emphasized that in order to set a new modulus value, the N DividerRegister must be written after the R Divider Register has changed. Thus writingto the R Divider Register implicates a subsequent write to the N Divider Register.This restriction exists due to the manufacturer’s specifications. The program I
2Most Significant Bit3Least Significant Bit
52
5.3 MSP430F149 Microcontroller Program
have developed for loading the register values to the ADF4153 takes this intoaccount by the byte order of the data block (refer to Section A.1 for the completeprogram listing). A valid programming sequence is therefore:
1. Send the ”R Divider Register” data.
2. Send the ”Control Register” data.
3. Send the ”Noise and Spur Register” data.
4. Send the ”N Divider Register” data.
5.3 MSP430F149 Microcontroller Program
The MSP430F149 controller from Texas Instruments is a 8/16-bit low-current devicewhich is equipped with 60 kB flash memory and 2 kB RAM. The program code Ihave developed stores the register data sets as constants in the µC memory. Twosets of 3-wire interface connections are driven simultaneously, one for program-ming the 1087,5 MHz synthesizer and a second for the 4252,5 MHz synthesizer.For this task, 6 pins of the µC port P1 are used as outputs. By starting the µCprogram, the data sets consisting of four 24-bit control words per synthesizer aretransferred to the PLL ICs automatically.
The program code is designed to fully support the µC low power mode: Afteran initialization sequuence, the controller is put in the energy-saving state LPM4.A timer-controlled interrupt service routine handles the data output at port P1.A timer is set up to generate interrupts at constant intervals to establish a timebasis for the clock signal CLK. On invocation, the ISR5 executes only the nec-essary commands to provide updated output, and the program causes the µC towait in LPM until the next CLK state change.
The program starts with basic initializations. The used port P1 register bitsare set up as outputs: P1.0 to P1.2 for the 1087,5 MHz synthesizer6 and P1.4 toP1.6 for the 4252,5 MHz synthesizer. Afterwards, registers used as loop variablesare initialized, namely r7 with the number of transmit bytes per data set and r12
containing the length of the ADF4153 shift register in bytes. Indirect addressingwith the value in r5 as offset is used to access the control data sets for bothsynthesizers, storing each read byte in r9 and r10, respectively. After one byte isprocessed, the offset value in r5 will be increased to point to the next data byte.Bit 0 of register r6 contains the CLK state, i.e. r6=1 indicates that CLK=high.The actual main program just waits in low-power mode for the timer interrupt.
4Low Power Mode5Interrupt Service Routine6Px.y denotes bit y of port x
53
5.3 MSP430F149 Microcontroller Program
For emphasis, important portions of the program code are presented here.A full listing is given in Section A.1. The first instructions set up the timer,enable interrupt triggering and declare the port 1 output bits. The suffix .b
induces an 8-bit access, while .w stands for 16-bit processing:
mov.w #WDTPW+WDTHOLD,&WDTCTL
bis.b #77h,&P1DIR
mov.w #CCIE,&CCTL0
mov.w #COUNT,&CCR0
mov.w #TASSEL_2+MC_2,&TACTL
The first data bytes are read from memory, the CLK output is set and the low-power mode is enabled with the following instructions:
mov.b send_me_1GHz(r5),r9
mov.b send_me_4GHz(r5),r10
mov.b #1,r6
mov.b &P1OUT,r15
and.b #0BBh,r15
bis.b #11h,r15
mov.b r15,&P1OUT
bis.w #CPUOFF+GIE,sr
nop
The code responsible for data readout and output resides in the interruptservice routine, which is invoked in regular intervals by the timer interrupt.
By the xor instruction in the following step bit 0 of register r6 is toggled.This register represents the CLK state.
toggle
xor.b #1,r6
mov.b r6,r14
rla.b r14
rla.b r14
rla.b r14
rla.b r14
bis.b r6,r14
mov.b &P1OUT,r15
and.b #0EEh,r15
bis.b r14,r15
mov.b r15,&P1OUT
In the subsequent steps, bit rotation is executed by the rla instructions. Theand instruction is used to clear only the associated CLK bits of r15, which holds
54
5.3 MSP430F149 Microcontroller Program
the value of register P1. By using the bis instruction, the CLK bits P1.0 andP1.4 of the 3-wire interface are updated.
The MSB of a control word must be sent first to the PLL IC. This is arrangedby rotating the data byte left through carry, i.e. the former MSB appears in thecarry bit. With the adc instruction, the bit is added to the cleared7 registerr4. Finally, the result is in turn rotated left one time to assign the 1087,5 MHzsynthesizer DATA output to P1.1.
xor r4,r4
rlc.b r9
adc.b r4
rla.b r4
In similar fashion, the 3-wire DATA bit for contacting the 4252,5 MHz synthesizeroccurs at port P1.5:
xor r11,r11
rlc.b r10
adc.b r11
rla.b r11
rla.b r11
rla.b r11
rla.b r11
rla.b r11
mov.b &P1OUT,r15
and.b #0DDh,r15
bis.b r4,r15
bis.b r11,r15
mov.b r15,&P1OUT
Now the clocking and data outputs of the 3-wire interface have been dealt with.Only the latch enable signal is left to be sent. Within the nested code loops,the LE output is set to indicate the complete transfer of 24 data bits into theADF4153 shift register.
mov.b #1,r13
mov.b &P1OUT,r15
bis.b #44h,r15
mov.b r15,&P1OUT
7all-zero
55
5.3 MSP430F149 Microcontroller Program
LE is cleared by:
mov.b &P1OUT,r15
and.b #0BBh,r15
mov.b r15,&P1OUT
xor.b r13,r13
Thus ports P1.2 and P1.6 form the LE output of the 3-wire interface.
Table 5.2 shows the associated controller ports for the 3-wire interfaces ofboth synthesizers.
Table 5.2: Mapping: Controller Ports to 3-Wire Interface.
The data sets to transfer are declared at the end of the program, for example,a valid data set for programming the 1087,5 MHz synthesizer is:
DB 10h, 7Fh, 0FDh
DB 00h, 0Ch, 62h
DB 00h, 03h, 0C7h
DB 0Dh, 98h, 00h
The data set is referenced by the address of the send_me_1GHz-label.
56
Chapter 6
Performance Measurements
In this chapter, both synthesizers LO1 and LO2 will be programmed to the cen-ter frequencies 1087,5 MHz and 4252,5 MHz, respectively. Each RF output isobserved by means of a spectrum analyzer to assess the synthesizer performance.Several synthesizer program setups are examined.
6.1 Setup
A synthesizer LO1 unit (f0,1 = 1087, 5 MHz) consists of the LO1 synthesizerPCB from Chapter 3, the power supply including the DC voltage regulator PCB(cf. Appendix A.3), and the microcontroller described in Chapter 5. These com-ponents are assembled within a 19-inch enclosure. Furthermore, a combination ofbandpass filter and amplifier on a separate PCB were added after the synthesizerPCB output.
Figure 6.1: Synthesizer Component Arrangement within the 19-Inch Enclosure.
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6.1 Setup
Figure 6.1 shows the arrangement of the synthesizer components within theenclosure. The upper left corner of the picture shows an RF power divider witheight outputs for both LO1 and LO2 (not used during the measurements). Pro-ceeding clockwise in Figure 6.1, the voltage supply PCB, the analog 12V sup-ply, the 4252,5MHz synthesizer PCB including an RF filter, the µC and the1087,5MHz synthesizer PCB can be seen.
There were no efforts to optimize the standardized analog 12V DC supplythat is also situated in the same 19-inch enclosure. Voltage noise filtering andstabilization were improved by the DC regulator PCB I have designed and built.The results in the next section can be considered as an overall synthesizer systemperformance1.
PC
B w
/ D
C
Reg
ula
tors
LO1
PCBLO2
PCB
19" Enclosure
uC 12V DC
Supply
Spectrum Analyzer
JTAG
AC Mains
4252,5 MHz1087,5 MHz
Network Bridge
LAN
PC
Matlab
GPIB
(terminated)
Figure 6.2: Synthesizer Hardware Setup for Measurement of LO1.
Figure 6.2 depicts the 19-inch synthesizer unit containing the LO1 and LO2circuit boards in the setup with the spectrum analyzer. The measurement datais read and stored by a workstation PC. A MATLAB program executed on a PCaccesses the spectrum analyzer by its GPIB interface. Further MATLAB codeserves to generate diagrams based on the data from the spectrum analyzer. Thefollowing measurements include the added bandpass filter and amplifier.
1To characterize the synthesizer circuit board alone, it must be operated within an envi-ronment of peak performance reference components. This affects the power supply as well asthe casing and the separate output amplifier. For this project, only the overall synthesizerperformance is of interest, hence the proposed setup.
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6.2 Results
6.2 Results
To verify the required operation, first LO1 is tuned to the center frequency f0. Iffref = 10 MHz, the expected output will occur at f0=1087,501832 MHz (cf. Chap-ter 3). For all measurements, the on-board 10 MHz oscillator (Section 3.2.1) isused as reference. The ADF4153 PLL IC is programmed as follows for a step sizeof fstep=4,884 kHz.
R Divider Register: prescaler=4/5, R = 1, F = 4095
N Divider Register: N = 54, K = 1536
Control Register: D = 2, Kφ = 313 µA · rad−1 (CP/2=1, CP CURRENT=0)
Noise and Spur Register: NOISE AND SPUR MODE = ”Lowest Noise Mode”
This results in fPFD = 20 MHz, ωc = 62, 204 · 103 s−1, and φ = 43, 4. The loopfilter components are as derived in Section 3.2.6.
Figure 6.3 shows the output spectrum of the LO1 synthesizer near the centerfrequency measured with the analyzer’s resolution bandwidth RBW = 100 Hz,i. e. the plot shows the power levels within a 100 Hz frequency band. Normalizingthis plot to a resolution bandwidth of RBW = 1 Hz gives the calculated powerspectral density expressed in dBc/Hz as shown in Figure 6.4.
Figure 6.4: Calculated LO1 Power Spectral Density: Lowest Noise Mode.
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6.2 Results
Now the performance of the LO2 synthesizer from Chapter 4 will be re-viewed. All presented output spectrum plots have been achieved with the loopfilter from Section 4.2.5. At first, operation at the required center frequencyf0 = 4252, 5 MHz with a step size of only fstep = 9, 768 kHz is examined. ThePLL IC register contents are derived from the parameters
R Divider Register: prescaler=8/9, R = 1, F = 4095
N Divider Register: N = 106, K = 1280
Control Register: D = 2, Kφ = 2, 5 mA · rad−1 (CP/2=1, CP CURRENT=111b)
Noise and Spur Register: NOISE AND SPUR MODE = ”Lowest Noise Mode”
for fPFD = 20 MHz, ωc = 64, 717 · 103 s−1, and φ = 50, 1. Figure 6.5 shows theoutput of the measurement with a resolution bandwidth RBW = 100 Hz, whichresults in the calculated power spectral density plot depicted in Figure 6.6.
The origin of the dual spurious spectral lines can be investigated by alteringthe software setup: when switching the register NOISE AND SPUR MODE to the”Lowest Spur Mode” optimization in an attempt to resolve the issue, both spursvanish. Unfortunately, the phase noise is raised in the process. This suggeststhat the ADF4153 PLL IC’s fractional interpolator strategy may be responsiblefor the unwanted spurious lines: the artifacts can be removed at the expense ofphase noise performance. A graphical comparison of the ”Lowest Spur Mode”and the original setup can be seen in Figure 6.7.
The appearance of the spurious artifacts depends on the chosen center fre-quency f0. There exist special cases of the synthesizer frequency programmingwhere no spurs occur: measurements for the parameters N = 106, K = 0 thatresult in f0 = 4240 MHz showed no spurious artifacts. In this special case, thecenter frequency f0 = 4240 MHz is an integer multiple of V · fPFD = 40 MHz.In Figure 6.8, a comparison of this special case measurement with the previouslyobtained result for f0 = 4252, 5 MHz is shown.
Figure 6.8: Measured LO2 Spectra in Lowest Noise Mode: RBW=100Hz.
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Summary
In this diploma thesis, I have designed and built two PLL circuits which areequipped with fractional-N frequency dividers. The circuits are programmablefrequency synthesizers and are used as local oscillators (LO) in a 5,2 GHz ra-dio system: I have designed the first synthesizer LO1 for a center frequencyof f0,1=1,0875GHz and the second synthesizer LO2 for a center frequency off0,2=4,2525GHz. The design process also included market research and partselection. The programmable fractional-N divider adds the flexibility that isrequired in rapid prototyping: the achieved smallest frequency step sizes offstep,1=4,884 kHz for LO1 and fstep,2=9,768 kHz for LO2, respectively, free theradio system from fixed channel raster constraints. The synthesizers feature anoutput frequency range of f0,1 ± 50MHz and f0,2 ± 25MHz, respectively. Foroperating the frequency synthesizers from a standard 12V supply, I have furtherdesigned and built a specialized voltage regulator board with multiple outputs.
Besides designing and building the synthesizer hardware, I have developedthe software for an extensive synthesizer control using a 8-/16-bit microcontrollerfrom Texas Instruments. My assembler program directly generates the required3-wire interface outputs at a microcontroller port.
Finally, I have characterized the synthesizers inside a 19-inch enclosure thatalso contains the microcontroller, an analog 12V power supply, and output ampli-fiers with filters. For both synthesizers, I have calculated the power spectraldensities based on the results of RF output spectrum measurements. For LO1,measured with the center frequency f0,1=1,0875GHz, the phase noise power spec-tral density is −90 dBc/Hz at |f − f0,1|=10 kHz. LO2 measurements with thecenter frequency f0,2=4,2525GHz yielded a phase noise power spectral density of−75 dBc/Hz at |f − f0,2|=10 kHz.
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Acknowledgments
I want to thank Arpad L. Scholtz and the Christian Doppler Laboratory formaking this diploma thesis possible. Also, many thanks go to my supervisorRobert Langwieser for his support throughout the diploma thesis.
Furthermore, I want to thank the friends and colleagues from university forthe good time and fruitful discussions.
My parents and family receive my respectful gratitude for their support of mystudies in many aspects.
[1] Floyd M. Gardner, Phaselock Techniques, John Wiley & Sons, Inc.Wiley-Interscience, 1979
[2] Roland Best, Theorie und Anwendungen des Phase-locked Loops, 5. Neu-auflage der Ausgabe 1987, AT-Verlag Aarau/Schweiz, 1993
[3] Ulrich L. Rohde, Microwave and Wireless Synthesizers: Theory and Design,Wiley-Interscience, October 1997
[4] Analog Devices, ADF4153 PLL Frequency Synthesizer, data sheet, Rev. A
[5] Analog Devices, ADF4153 PLL Frequency Synthesizer, data sheet, Rev. Bhttp://www.analog.com/UploadedFiles/Data Sheets/ADF4153.pdf
[6] Analog Devices, Evaluation Board For Fractional-N PLL Frequency Synthe-sizer, tech notehttp://www.analog.com/Analog Root/static/techSupport/designTools/
5.1 Truth Table of the Control Bits C2 and C1. . . . . . . . . . . . . 495.2 Mapping: Controller Ports to 3-Wire Interface. . . . . . . . . . . . 56
A.1 Part List for the f0=1087,5 MHz Synthesizer PCB. . . . . . . . . 74A.2 Part List for the f0=4252,5 MHz Synthesizer PCB. . . . . . . . . 79A.3 Part List for the Voltage Supply PCB. . . . . . . . . . . . . . . . 84
