PHYTEC Meßtechnik GmbH
Robert-Koch-Straße 39 • D-55129 MainzTelefon: +49-(0)6131/9221-0Telefax: +49-(0)6131/9221-33Internet: http://www.phytec.com
PHYTEC Meßtechnik GmbH • Postfach 100403 • D-55135 Mainz
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Geschäftsführer: Dipl.-Ing. Michael Mitezki • Handelsregister Mainz, HRB 4656
Ein Unternehmen der PHYTEC Technologie Holding Aktiengesellschaft
Information for our customers
Mainz, 05.06.2002
With regard to: Second CAN interface of the phyCORE-DS80C390PCB-Version 3087.0
Dear Customer,
The phyCORE-DS80C390 (PCM-015) will initially be delivered in PCB version 3087.0. Due toan error in the microcontroller data sheet, the second CAN interface of the DS80C390 cannot beused as described in the hardware manual L-594e_1.pdf.
1. Signals of CAN1 with TTL level
If the CAN1 interface signals are to be used with their TTL level, it is important to be aware thatthe CANRxD1 signal (P5.2) is not routed to CANH1 (phyCORE Pin X1D13) but rather toCANL1 (phyCORE Pin X1D12). Vice-versa, CANTxD1 is not routed on CANL1 (phyCOREPin X1D12), instead it is available on CANH1 (phyCORE Pin X1D13). The second CANtransceiver U3 on the Development Board can therefore not be used. When using the CAN1interface with a TTL level it is important to make sure that the internal CAN transceiver U12 ofthe phyCORE-DS80C390 is not connected to P5.2 or P5.3. Therefore the handwiring of JumpersJ16/J17 must be open (see below).
This error will be eliminated in the PCB version 3087.1.
2. Signals of CAN1 via internal CAN transceiver
The TTL signals CANRxD1 (P5.2) and CANTxD1 (P5.3) from port CAN1 of themicrocontroller are not properly connected to the CAN transceiver U12. Upon delivery the CANtransceiver U12 is connected correctly to the signals CANRxD1 and CANTxD1 via two hand-wires.
• Jumpers J16 and J17 are not connected• Pin 1 on J16 is connected to Pin 2 on J17 via hand-wiring• Pin 1 on J17 is connected to Pin 2 on J16 via hand-wiring
This error will be eliminated in the next PCB version 3087.1. In the new PCB version theJumpers J16/J17 can be used as described in the current hardware manual L-594e_1.
Please contact PHYTEC at [email protected] (for customers in North America) [email protected] (for customers in Europe) with any additional questions.
Many friendly regards,PHYTEC Meßtechnik GmbH
A product of a PHYTEC Technology Holding company
phyCORE-DS80C390
Hardware Manual
Edition April 2002
phyCORE-DS80C390
PHYTEC Meßtechnik GmbH 2002 L-594e_1
In this manual are descriptions for copyrighted products that are not explicitlyindicated as such. The absence of the trademark () and copyright () symbolsdoes not imply that a product is not protected. Additionally, registered patents andtrademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to beentirely reliable. However, PHYTEC Meßtechnik GmbH assumes noresponsibility for any inaccuracies. PHYTEC Meßtechnik GmbH neither gives anyguarantee nor accepts any liability whatsoever for consequential damages resultingfrom the use of this manual or its associated product. PHYTEC MeßtechnikGmbH reserves the right to alter the information contained herein without priornotification and accepts no responsibility for any damages which might result.
Additionally, PHYTEC Meßtechnik GmbH offers no guarantee nor accepts anyliability for damages arising from the improper usage or improper installation ofthe hardware or software. PHYTEC Meßtechnik GmbH further reserves the rightto alter the layout and/or design of the hardware without prior notification andaccepts no liability for doing so.
Copyright 2002 PHYTEC Meßtechnik GmbH, D-55129 Mainz.Rights - including those of translation, reprint, broadcast, photomechanical orsimilar reproduction and storage or processing in computer systems, in whole or inpart - are reserved. No reproduction may occur without the express written consentfrom PHYTEC Meßtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AGRobert-Koch-Str. 39D-55129 MainzGERMANY
PHYTEC America LLC255 Ericksen Avenue NEBainbridge Island, WA 98110USA
OrderingInformation:
+49 (800) [email protected]
1 (800) [email protected]
TechnicalSupport:
+49 (6131) [email protected]
1 (800) [email protected]
Fax: +49 (6131) 9221-33 1 (206) 780-9135
Web Site: http://www.phytec.de http://www.phytec.com
1st Edition: April 2002
Contents
PHYTEC Meßtechnik GmbH 2002 L-594e_1
Preface ......................................................................................................1
1 Introduction .........................................................................................3
1.1 Block Diagram..............................................................................6
1.2 View of the phyCORE-DS80C390...............................................7
2 Pin Description.....................................................................................9
3 Jumpers ..............................................................................................15
3.1 J1 Internal or External Program Memory..................................18
3.2 J2 Supply Voltage for SRAMs U3/U4 .......................................18
3.3 J3, J4, J5 SRAM Configuration.................................................19
3.4 J6, J7 /PCE2 and /PCE3 Configuration .....................................19
3.5 J8, J9, J10 Serial Interface Configuration..................................20
3.6 J13 Interrupt Output of the RTC................................................21
3.7 J14, J15 I2C Bus Configuration ................................................21
3.8 J18, J19, J20, J21 First CAN Interface Configuration...............22
3.9 J11, J12, J16, J17 Second CAN Interface Configuration ..........23
3.10 J22 RTC Clockout .....................................................................23
4 Memory Models .................................................................................25
4.1 Address Decoder Control Registers............................................30
5 Serial Interfaces .................................................................................33
5.1 RS-232 Interface.........................................................................33
5.2 RS-485 Interface.........................................................................33
5.3 CAN Interface.............................................................................34
6 Flash Memory (U5)............................................................................35
7 Serial EEPROM (U7) ........................................................................38
8 Real-Time Clock RTC-8564 (U6).....................................................39
9 Reset Controller (U8) ........................................................................40
10 Remote Supervisory Chip (U9) ........................................................41
11 Battery Buffer ....................................................................................42
12 Technical Specifications....................................................................43
13 Hints for Handling the Module ........................................................45
phyCORE-DS80C390
PHYTEC Meßtechnik GmbH 2002 L-594e_1
14 The phyCORE-DS80C390 on the phyCORE
Development Board LD 5V .............................................................. 47
14.1 Concept of the phyCORE Development Board LD 5V ............. 47
14.2 Development Board LD 5V Connectors and Jumpers ............... 49
14.2.1 Connectors..................................................................... 49
14.2.2 Jumpers on the phyCORE
Development Board LD 5V .......................................... 50
14.2.3 Unsupported Features and Improper Jumper Settings .. 52
14.3 Functional Components on the phyCORE
Development Board LD 5V........................................................ 53
14.3.1 Power Supply at X1....................................................... 53
14.3.2 Starting FlashTools ....................................................... 55
14.3.3 First Serial Interface at Socket P1A .............................. 57
14.3.4 Socket P1B .................................................................... 58
14.3.5 First CAN Interface at Plug P2A................................... 60
14.3.6 RS-485 Interface or Second CAN Interface at
Plug P2B........................................................................ 66
14.3.7 Programmable LED D3................................................. 74
14.3.8 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field. .............................. 75
14.3.9 Battery Connector BAT1............................................... 80
14.3.10 DS2401 Silicon Serial Number ..................................... 81
14.3.11 Pin Header Connector X4 ............................................. 82
Index .................................................................................................... 83
Contents
PHYTEC Meßtechnik GmbH 2002 L-594e_1
Index of Figures and Tables
Figure 1: Block Diagram..............................................................................6
Figure 2: Top View of the phyCORE-DS80C390 .......................................7
Figure 3: Bottom View of the phyCORE-DS80C390..................................7
Figure 4: Pinout of the phyCORE-DS80C390 (Top View) .........................9
Figure 5: Numbered Matrix Overview of the phyCORE-Connector(Viewed from Above).................................................................11
Figure 6: Numbering of the Jumper Pads...................................................15
Figure 7: Location of the Jumpers (Top View)..........................................15
Figure 8: Location of the Jumpers (Bottom View) ....................................16
Figure 9: Runtime Memory Model Following a Hardware Reset(Boot not Active) ........................................................................26
Figure 10: Von Neumann Memory Model...................................................27
Figure 11: Programming Model Following a Hardware Reset(Boot Active) ..............................................................................29
Figure 12: Memory Areas of the Flash Device ............................................36
Figure 13: Physical Dimensions (not Shown at Scale) ................................43
Figure 14: Modular Development and Expansion Board Conceptwith the phyCORE-DS80C390...................................................48
Figure 15: Location of Connectors on the phyCOREDevelopment Board LD 5V........................................................49
Figure 16: Numbering of Jumper Pads ........................................................50
Figure 17: Location of the Jumpers (View of the Component Side) ...........51
Figure 18: Default Jumper Settings of the phyCOREDevelopment Board LD 5V with phyCORE-DS80C390 ...........51
Figure 19: Connecting the Supply Voltage at X1 ........................................54
Figure 20: Pin Assignment of the DB-9 Socket P1A as RS-232(Front View) ...............................................................................57
Figure 21: Pin Assignment of the DB-9 Socket P1B (Front View) .............58
phyCORE-DS80C390
PHYTEC Meßtechnik GmbH 2002 L-594e_1
Figure 22: Pin Assignment of the DB-9 Plug P2A (CAN Transceiveron phyCORE-DS80C390) .......................................................... 60
Figure 23: Pin Assignment of the DB-9 Plug P2A (CAN Transceiveron Development Board) ............................................................. 62
Figure 24: Pin Assignment of the DB-9 Plug P2A (CAN Transceiveron Development Board with Galvanic Separation).................... 65
Figure 25: Pin Assignment of the DB-9 Plug P2B (CAN Transceiveron phyCORE-DS80C390) .......................................................... 67
Figure 26: Pin Assignment of the DB-9 Plug P2B (CAN Transceiveron Development Board) ............................................................. 68
Figure 27: Pin Assignment of the DB-9 Plug P2B (CAN Transceiveron Development Board with Galvanic Separation).................... 71
Figure 28: Pin Assignment of the DB-9 Plug P2B as RS-485 Interface ..... 72
Figure 29: Pin Assignment Scheme of the Expansion Bus.......................... 76
Figure 30: Pin Assignment Scheme of the Patch Field................................ 76
Figure 31: Connecting the DS2401 Silicon Serial Number......................... 82
Figure 32: Pin Assignment of the DS2401 Silicon Serial Number.............. 82
Table 1: Pinout of the phyCORE-Connector............................................ 14
Table 2: Jumper Settings Overview.......................................................... 17
Table 3: J1 Code Fetch Selection ............................................................ 18
Table 4: J2 SRAM Supply Voltage Configuration.................................. 18
Table 5: J3, J4, J5 SRAM Configuration................................................. 19
Table 6: J6, J7 /PCE2 and /PCE3 Configuration..................................... 20
Table 7: J8, J9, J10 Serial Interface Configuration ................................. 20
Table 8: J13 RTC Interrupt Configuration .............................................. 21
Table 9: J14, J15 I²C Bus Configuration ................................................. 22
Table 10: J18, J19, J20 and J21 CAN0 Interface Configuration................ 22
Table 11: J11, J12, J16 and J17 CAN1 Interface Configuration................ 23
Table 12: J22 RTC Clockout Configuration.............................................. 23
Table 13: Control Register 1 of the Address Decoder................................ 30
Contents
PHYTEC Meßtechnik GmbH 2002 L-594e_1
Table 14: Control Register 2 of the Address Decoder................................31
Table 15: Control Register 3 of the Address Decoder................................31
Table 16: Flash Memory and Manufacturer Overview...............................35
Table 17: Memory Device Options at U7...................................................38
Table 18: Improper Jumper Settings for the Development Board..............52
Table 19: JP9 Configuration of the Main Supply Voltage VCCI...............53
Table 20: JP9 Improper Jumper Settings for the Main Supply Voltage .....54
Table 21: JP28 Configuration of the Boot Button ......................................55
Table 22: JP28 Configuration of a Permanent FlashToolsStart Condition............................................................................56
Table 23: JP22, JP23, JP10 Configuration of Boot via RS-232 .................56
Table 24: Improper Jumper Settings for Boot via RS-232 .........................56
Table 25: Jumper Configuration for the RS-232 Interface .........................57
Table 26: Jumper Configuration of the DB-9 Socket P1B .........................58
Table 27: Improper Jumper Settings for Configuration of P1B .................59
Table 28: Jumper Configuration for CAN Plug P2A using theCAN Transceiver on the phyCORE-DS80C390 ........................60
Table 29: Improper Jumper Settings for the CAN Plug P2A(CAN Transceiver on phyCORE-DS80C390)............................61
Table 30: Jumper Configuration for CAN Plug P2A using theCAN Transceiver on the Development Board............................62
Table 31: Improper Jumper Settings for the CAN Plug P2A(CAN Transceiver on the Development Board) .........................63
Table 32: Jumper Configuration for CAN Plug P2A using theCAN Transceiver on the Development Board withGalvanic Separation....................................................................64
Table 33: Improper Jumper Settings for the CAN Plug P2A(CAN Transceiver on Development Board withGalvanic Separation) ..................................................................65
Table 34: Jumper Configuration for CAN Plug P2B using theCAN Transceiver on the phyCORE-DS80C390 ........................66
phyCORE-DS80C390
PHYTEC Meßtechnik GmbH 2002 L-594e_1
Table 35: Improper Jumper Settings for the CAN Plug P2B(CAN Transceiver on phyCORE-DS80C390) ........................... 67
Table 36:Jumper Configuration for CAN Plug P2B using theCAN Transceiver on the phyCORE-DS80C390 ........................ 68
Table 37: Improper Jumper Settings for the CAN Plug P2B(CAN Transceiver on the Development Board)......................... 69
Table 38: Jumper Configuration for CAN Plug P2B using theCAN Transceiver on the Development Board withGalvanic Separation ................................................................... 70
Table 39: Improper Jumper Settings for the CAN Plug P2B(CAN Transceiver on Development Board withGalvanic Separation) .................................................................. 71
Table 40: Jumper Configuration for DB-9 Plug P2B asRS-485 Interface......................................................................... 72
Table 41: Improper Jumper Settings for the RS-485 Interface atPlug P2B..................................................................................... 73
Table 42: JP17 Configuration of the Programmable LED D3 ................... 74
Table 43: Pin Assignment Data/Address Bus for thephyCORE-DS80C390 / Development Board /Expansion Board ........................................................................ 77
Table 44: Pin Assignment Control Signals for thephyCORE-DS80C390 / Development Board /Expansion Board ........................................................................ 78
Table 45: Pin Assignment Interface Signals for thephyCORE-DS80C390 / Development Board /Expansion Board ........................................................................ 78
Table 46: Pin Assignment Power Supply for thephyCORE-DS80C390 / Development Board /Expansion Board ........................................................................ 79
Table 47: Unused Pins on the phyCORE-DS80C390 /Development Board / Expansion Board ..................................... 80
Table 48: JP19 JumperConfiguration for Silicon Serial Number Chip...... 81
Preface
PHYTEC Meßtechnik GmbH 2002 L-594e_1 1
Preface
This phyCORE-DS80C390 Hardware Manual describes the board’sdesign and functions. Precise specifications for the Dallas DS80C390microcontroller can be found in the enclosed microcontroller DataSheet/User’s Manual. If software is included please also refer toadditional documentation for this software.
In this hardware manual and in the attached schematics, low activesignals are denoted by a "/" in front of the signal name (i.e.: /RD). A"0" indicates a logic-zero or low-level signal, while a "1" represents alogic-one or high-level signal.
Declaration of Electro Magnetic Conformity for thePHYTEC phyCORE-DS80C390
PHYTEC Single Board Computers (henceforth products) are designedfor installation in electrical appliances or as dedicated EvaluationBoards (i.e.: for use as a test and prototype platform forhardware/software development) in laboratory environments.
Note:PHYTEC products lacking protective enclosures are subject to dam-age by Electro Static Discharge (ESD) and, hence, may only beunpacked, handled or operated in environments in which sufficientprecautionary measures have been taken in respect to ESD dangers. Itis also necessary that only appropriately trained personnel (such aselectricians, technicians and engineers) handle and/or operate theseproducts. Moreover, PHYTEC products should not be operatedwithout protection circuitry if connections to the product’s pin headerrows are longer than 3 m.
phyCORE-DS80C390
2 PHYTEC Meßtechnik GmbH 2002 L-594e_1
PHYTEC products fulfill the norms of the European Union’sDirective for Electro Magnatic Conformity only in accordance to thedescriptions and rules of usage indicated in this hardware manual(particularly in respect to the pin header row connectors, powerconnector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well asuser modifications and extensions of PHYTEC products, is subject torenewed establishment of conformity to, and certification of, ElectroMagnetic Directives. Users should ensure conformance following anymodifications to the products as well as implementation of theproducts into target systems.
The phyCORE-DS80C390 is one of a series of PHYTEC SingleBoard Computers (SBCs) that can be populated with differentcontrollers and, hence, offers various functions and configurations.PHYTEC supports all common 8- and 16-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as areference and evaluation platform
(2) as insert-ready, fully functional micro- / mini- and phyCOREOEM modules which can be embedded directly into the user'speripheral hardware design.
PHYTEC's microcontroller modules allow engineers to shorten devel-opment horizons, reduce design costs and speed project concepts fromdesign to market.
Introduction
PHYTEC Meßtechnik GmbH 2002 L-594e_1 3
1 Introduction
The phyCORE-DS80C390 belongs to PHYTEC’s phyCORE SingleBoard Computer (SBC) module family. The phyCORE SBCsrepresent the continuous development of PHYTEC Single BoardComputer technology. Like its mini-, micro- and nanoMODULpredecessors, the phyCORE boards integrate all core elements of amicrocontroller system on a subminiature board and are designed in amanner that ensures their easy expansion and embedding in peripheralhardware developments.
As independent research indicates that approximately 70 % of allElectro Magnetic Interference (EMI) problems stem from insufficientsupply voltage grounding of electronic components in high frequencyenvironments, the phyCORE board design features an increased pinpackage. The increased pin package allows dedication ofapproximately 20 % of all pin header connectors on the phyCOREboards to Ground. This improves EMI and EMC characteristics andmakes it easier to design complex applications meeting EMI andEMC guidelines using phyCORE boards even in high noise environ-ments.
phyCORE modules achieve their small size through advanced SMDtechnology and multi-layer design. In accordance with the complexityof the module, 0402-packaged SMD and laser-drilled Microviascomponents are used on the boards, providing phyCORE users withaccess to this cutting edge miniaturization technology for integrationinto their own design.
phyCORE-DS80C390
4 PHYTEC Meßtechnik GmbH 2002 L-594e_1
The phyCORE-DS80C390 is a subminiature (55 x 47.5 mm) insert-ready Single Board Computer populated with the DallasSemiconductors DS80C390 microcontroller featuring dual on-chip2.0B CAN and a 16/32 arithmetic coprocessor. Its universal designenables its insertion in a wide range of embedded applications. Allcontroller signals and ports extend from the controller tostandard-width (2.54 mm / 0.1 in.) pin header rows aligning two sidesof the board, allowing it to be plugged like a "big chip" into a targetapplication.
Precise specifications for the controller populating the board can befound in the applicable controller User’s Manual or Data Sheet. Thedescriptions in this manual are based on the DS80C390microcontroller. No description of compatible microcontrollerderivative functions is included, as such functions are not relevant forthe basic functioning of the phyCORE-DS80C390.
Introduction
PHYTEC Meßtechnik GmbH 2002 L-594e_1 5
The phyCORE-DS80C390 offers the following features:
• subminiature Single Board Computer (55 x 47.5 mm) achievedthrough advanced SMD technology
• populated with the Dallas DS80C390 microcontroller (QFP-64packaging) featuring two CAN 2.0B controllers
• instruction cycle time of 100 ns at 10 MHz clock speed inX4 mode
• improved interference safety achieved through multi-layer PCBtechnology and dedicated Ground pins
• controller signals and ports extend to standard-width (2.54 mm)pins aligning two sides of the board, enabling it to beconnectorged like a "big chip" into target applications
• 256 kByte to 2 MByte on-board1 SMD Flash, enabling In-SystemProgramming (ISP) with PHYTEC FlashTools
• no dedicated Flash programming voltage required through use of5 V Flash devices
• 128 kByte to 1 MByte external SRAM on-board (SMD)1
• flexible software-configurable address decoding via a complexlogic device
• bank latches for Flash and SRAM integrated in address decoder• RS-232 or RS-485 interface, user-configurable• two CAN interfaces with dual on-board 82C251 CAN transceiver• I²C Real-Time Clock• 4 kByte I²C EEPROM• Watchdog device for reset logic and battery control• Remote Supervisory Circuit2
• free Chip Select signals for easy connection of peripheral devices• requires single 5 V / < 200 mA supply voltage
1 : For more information about additional configurations please contact PHYTEC.2 : This feature is under development and not available yet.
phyCORE-DS80C390
6 PHYTEC Meßtechnik GmbH 2002 L-594e_1
1.1 Block Diagram
Figure 1: Block Diagram
digital ports
I2C Interface
CAN0Rx, CAN0Tx
RxD
RESET
CAN0
/CS[3..1]AddressDecoder
FLASH SRAM
Micro-controller
VoltageSupervisor
RemoteSupervisor
EEPROM
phyCORE-Connector
CANTransceiver
(U3/U4)128kB..1 MB
(U5)256kB. .2MB (U2)
(U9)(U8)
(U13)
(U1)
(U7)
Dallas
Semiconductor
DS80C390
1
2
1 phyCORE-specific
2 This feature is under development and is not available yet.
RTC(U6)
S0RxD, S0TxD
RS-232RS-232Transceiver
(U10)
RS-485RS-485Transceiver
(U11)
CAN1Rx, CAN1Tx CAN1CANTransceiver
(U12)
/CS-Unit
Introduction
PHYTEC Meßtechnik GmbH 2002 L-594e_1 7
1.2 View of the phyCORE-DS80C390
Figure 2: Top View of the phyCORE-DS80C390
Figure 3: Bottom View of the phyCORE-DS80C390
PIN 1 A B FEDC
1
16
14
3
2
45678910111213
15
D3
XT1
U11
U3
U1
CB11
16
14
32
45678910111213
15
CB59
CB58
CB3
CB9
U5
CB53 CB8
J2
J16
J17
J18
J19
J11
J21
J20
J12
J9
J10
J8J16
J17
R5
C4
CB2
CB52
J1
C2
C1
R1J6 J7 R18
U9
Q3
CB51
R7
R10
R11R2 R8J13
PIN 1
1
16
14
32
4
56
78
910
11
1213
15
1
16
14
32
4
56
78
910
11
1213
15U4
U13 C3
CB7
CB57 R4
U12
C3
CB56
CB55 R21 R22
C10
C7
C8
C9
C5
Q4
U10
U7
J3
J4
J5
R3
CB6
U2
CB54CB5R6
CB10
CB4CB60
R17
C12
C11
Q5
C13
R15
R9 D2
U6
R13
Q2
Q3
U8
D1C6
R14
R19
R20
R12
R16
phyCORE-DS80C390
8 PHYTEC Meßtechnik GmbH 2002 L-594e_1
Pin Description
PHYTEC Meßtechnik GmbH 2002 L-594e_1 9
2 Pin Description
Please note that all module connections are not to exceed theirexpressed maximum voltage or current. Maximum signal input valuesare indicated in the corresponding controller User’s Manual/DataSheets located on the Spectrum CD. As damage from improperconnections varies according to use and application, it is the user'sresponsibility to take appropriate safety measures to ensure that themodule connections are protected from overloading throughconnected peripherals.
As Figure 4 indicates, all controller signals extend to standard-width(2.54 mm / 0.1 in.) pin rows lining two sides the board (referred to asphyCORE-connector). This allows the phyCORE-DS80C390 to beplugged into any target application like a "big chip".
Figure 4: Pinout of the phyCORE-DS80C390 (Top View)
A new numbering scheme for the pins on the phyCORE-connectorhas been introduced with the phyCORE specifications. This enablesquick and easy identification of desired pins and minimizes errorswhen matching pins on the phyCORE module with the receptaclesocket on the appropriate PHYTEC phyCORE DevelopmentBoard LD 5V or your OEM application.
P I N 1 A B FEDC
1
1 6
1 4
3
2
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 5
C L K I N / I N T 0
/ I N T 1 G N D
G N D / C S 1
/ C S 2 A L E / C S 3
/ R D G N D / W R
A 0 A 1 A 2
A 3 G N D A 4
A 5 G N D A 6
A 7 A 8 A 9
A 1 0 G N D A 1 1
A 1 2 A 1 3 A 1 4
A 1 5 G N D A D 0
A D 1 G N D A D 2
A D 3 A D 4 A D 5
A D 6 G N D A D 7
A 1 6 A 1 7 A 1 8
1
1 6
1 4
3
2
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 5
V C C V C C G N D
N C N C G N D
N C N C G N D
V B A T V P D P F I
W D I G N D P F O
B O O T / R E S / R E S
G N D P 4 2
T 1 G N D
G N D
P 3 0 P 3 1
C A N L 1 G N D
C A N H 1 G N D B
C A N H 0
A T x D 0C A N L 0
G N D R x D 0
P C E 2A 1 9 P C E 3
T 0
N C
N C
N C
N C
S C L
S D A
N C N C
N C N C
N C
phyCORE-DS80C390
10 PHYTEC Meßtechnik GmbH 2002 L-594e_1
The numbering scheme for the phyCORE-connector is based on a twodimensional matrix in which column positions are identified by aletter and row position by a number. Pin 1A, for example, is alwayslocated in the upper left hand corner of the matrix. The pin numberingvalues increase moving down on the board. Lettering of the pinconnector rows progresses alphabetically from left to right(refer to Figure 5).
The numbered matrix can be aligned with thephyCORE-DS80C390 (viewed from above; phyCORE-connectorheader pins pointing down) or with the socket of the phyCOREDevelopment Board LD 5V / target circuitry. The upper left-handcorner of the numbered matrix (Pin 1A) is thus covered with thecorner of the phyCORE-DS80C390 marked with a white triangle. Thenumbering scheme is always in relation to the PCB as viewed fromabove, even if all contacts extend to the bottom of the board.
The numbering scheme is thus consistent for both the module’sphyCORE-connector as well as mating connectors on the phyCOREDevelopment Board LD 5V or target hardware, thereby considerablyreducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrixpreviously described, the phyCORE-connector’s receptacle socket isusually assigned a single designator for its position (X1 for example).In this manner the phyCORE-connector comprises a single, logicalunit regardless of the fact that it could consist of more than onephysical connector. The location of row 1 on the board is marked by awhite triangle on the PCB to allow easy identification.
Pin Description
PHYTEC Meßtechnik GmbH 2002 L-594e_1 11
The following figure (Figure 5) illustrates the numbered matrixsystem. It shows a phyCORE-DS80C390 mounted on a phyCOREDevelopment Board LD 5V. The shaded area of the phyCORE-connectors shown below indicates the remaining pins not used inconjunction with the phyCORE-DS80C390 which, when pluggedonto the Development Board, does not span the entire length of thereceptacle socket. The phyCORE Development Board LD 5V canhouse all phyCORE modules with standard-width (2.54 mm / 0.10 in)pin header rows and a maximum of 32 pins per pin header row, A, B,C, D, E and F.
Figure 5: Numbered Matrix Overview of the phyCORE-Connector(Viewed from Above)
Many of the controller port pins accessible at header pins along theedges of the board have been assigned alternate functions that can beactivated via software.
A B C1 1
D E F
phyCORE-DS80C390
12 PHYTEC Meßtechnik GmbH 2002 L-594e_1
Table 1 provides an overview of the pinout of the phyCORE-connector and shows possible alternative functions of the pins. Pleaserefer to the microcontroller User’s Manual/Data Sheet for details onthe functions and features of controller signals and port pins.
Pin Number Signal I/O DescriptionPin Row X1A
1A ClkIn I Optional external clock generator inputconnected directly to XTAL1 of µC
2A P3.3/INT1 I/O Port pin µC3A NC - not connected4A /CS2 O Pre-decoded Chip Select signal #25A /RD O /RD signal
6A, 7A, 8A,9A, 10A, 11A,
12A, A16
A0, A3, A5,A7, A10, A12,A15, A16
O Address bus from address latch(A0, A3, A5, A7, A10, A12, A15, A16)
13A, 14A,5A
AD1, AD3,AD6
O Multiplexed address/data bus from µC
Pin Row X1B1B NC - not connected
2B, 3B, 5B, 7B,8B, 10B, 12B,
13B, 15B
GND - Ground 0 V
4B ALE O Address Latch Enable output µC6B, 9B,
11B, 16BA1, A8,A13, A17
O Address bus from address latch(A1; A8; A13, A17)
14B AD4 I/O Multiplexed address/data bus from µCPin Row X1C
1C P3.2 / /INT0 I/O Port pin µC2C NC - not connected
3C, 4C /CS1, /CS3 O Pre-decoded Chip Select signal #1, #35C /WR, P3.6 I/O /WR signal µC
6C, 7C, 8C,9C, 10C,11C, 16C
A2, A4, A6,A9, A11,A14, A18
O Address bus from address latch(A2; A4; A6; A9; A11; A14; A18)
12C, 13C,4C, 15C
AD0, AD2,AD5, AD7
I/O Multiplexed address/data bus µC
Pin Description
PHYTEC Meßtechnik GmbH 2002 L-594e_1 13
Pin Number Signal I/O DescriptionPin Row X1D
1D VCC - Voltage input +5 VDC2D, 3D, 10D NC - not connected
4D VBAT I Input for connection to external bufferbattery (+)
5D WDI I WDI input of the Reset controller6D BOOT I Boot = 1 during Reset → starts the Boot
sequence7D,8D,9D,11D
P3.4 (T0),P3.5 (T1),P4.3,P3.0 (RxD)
I/O Port pins of the microcontroller
12D CANL1,P5.2 (C1Tx)
I/O CANL signal of CAN transceiver U12, orPort pin of the microcontroller
13D CANHP5.3 (C1Rx)
I/O CANH signal of CAN transceiver U12, orPort pin of the microcontroller
14D CANL0,P5.0 (C0Tx)
I/O CANL signal of CAN transceiver U13, orPort pin of the microcontroller
15D CANH0P5.1 (C0Rx)
I/O CANH signal of CAN transceiver U13, orPort pin of the microcontroller
15D A19 O Address line A19Pin Row X1E
1E VCC - Voltage input +5 V2E, 3E NC - not connected
4E VPD O Voltage output for external buffer (+)5E, 7E, 8E,10E, 12E,13E, 15E
GND - Ground 0 V
6E /RES O Reset output of the module,directly connected with Reset input
9E,11E
P1.4,P3.1 (TxD)
I/O Port pins of the microcontroller
14E A I/O Differential A signal of the RS-485 transceiver16E /PCE2 (P5.6) I/O Chip Select signal or port pin of the
microcontroller
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Pin Row X1F1F, 2F, 3F GND - Ground 0 V
4F PFI I Power Fail Input of Reset IC5F /PF0 O Power Fail Output of Reset IC6F /RES I Reset input of the module7F /RESOUT O Reset output of the microcontroller8F P4.2 I/O Port pin of the microcontroller9F NC - not connected
10F CLKRTC O RTC clock output11F,12F
SCL,SDA
I/O I²C bus signals SCL (clock) andSDA (data)
13F B I/O Differential B signal of the RS-485 transceiver14F TxD0 O Transmit output of the RS-232 transceiver15F RxD0 I Receive input of the RS-232 transceiver16F /PCE3 (P5.7) I/O Chip Select signal or port pin of the
microcontroller
Table 1: Pinout of the phyCORE-Connector
Jumpers
PHYTEC Meßtechnik GmbH 2002 L-594e_1 15
3 Jumpers
For configuration purposes, the phyCORE-DS80C390 has 22 solderjumpers, some of which have been installed prior to delivery.Figure 6 illustrates the numbering of the jumper pads, while Figure 7and indicate the location of the jumpers on the board.
1
23
1
2
e.g.: J1, ... e.g.: J14, ..
Figure 6: Numbering of the Jumper Pads
Figure 7: Location of the Jumpers (Top View)
P I N 1 A B FEDC
1
1 6
1 4
3
2
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 5
U 1 1
U 3
U 1
1
1 6
1 4
3
2
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 5
U 5
J 2
J 1 6J 1 7J 1 8J 1 9
J 1 1
J 2 1J 2 0
J 1 2
J 9J 1 0
J 8J 1 6J 1 7
J 1
J 6 J 7
U 9J 1 3
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Figure 8: Location of the Jumpers (Bottom View)
PIN 1
1
16
14
32
45678910111213
15
1
16
14
32
45678910111213
15U4
U13
U12
U10
U7
J3
J4
J5
U2
U6
U8
Jumpers
PHYTEC Meßtechnik GmbH 2002 L-594e_1 17
The jumpers (J = solder jumper) have the following functions:
Default Setting Alternative SettingJ1 (1+2) external ROM/ Flash
active(2+3) internal ROM/Flash
activeJ2 (1+2) VPD supplies SRAMs at
U3 and U4(2+3) VCC supplies SRAMs at
U3 and U4J3 (1+2) /CS_RAM = 128 kByte (2+3) /CS_RAM = 512 kByteJ4 (1+2) SRAM U3 = 128 kByte (2+3) SRAM U3 = 512 kByteJ5 (1+2) SRAM U4 = 128 kByte (2+3) SRAM U4 = 512 kByteJ6 (1+2) P5.6 = /PCE2 (2+3) P5.6 = port pinJ7 (1+2) P5.7 = /PCE3 (2+3) P5.7 = port pinJ8,J9
(1+2) UART signals connect(1+2) to RS-232 transceiver
at U10
(2+3) UART signals connect(2+3) to RS-485 transceiver
at U11J10 (1+2) P3.5 actives RS-485
transceiver(2+3) RS-485 transceiver always
active(open) RS-485 transceiver
disabledJ11,J12
(1+2) CANL1 at X1D12(1+2) CANH1 at X1D13
(2+3) P5.2 (C1Tx) at X1D12(2+3) P5.3 (C1Rx) at X1D13
J13 (closed) /INTRTC connected with P3.2
(open) /INTRTC not used
J14,
J15
(closed) I²C bus connected to port P4.2 (SCL) and
(closed) port P4.3 (SDA)
(open) external I²C bus can be connected to X1F11 (SCL)
(open) and X1F12 (SDA)J16,J17
(closed) P5.2 as TxDC1 at U12(closed) P5.3 as RxDC1 at U12
(open) P5.2 = port pin(open) P5.3 = port pin
J18,J19
(closed) P5.0 as TxDC0 at U13(closed) P5.1 as RxDC0 at U13
(open) P5.0 = port pin(open) P5.1 = port pin
J20,J21
(1+2) CANL0 at X1D14(1+2) CANH0 at X1D15
(2+3) P5.0 (C0Tx) at X1D14(2+3) P5.1 (C0Rx) at X1D15
J22 (1+2) RTC clockout not active (2+3) RTC clockout active
Table 2: Jumper Settings Overview
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3.1 J1 Internal or External Program Memory
At the time of delivery, Jumper J1 is closed at pads 1+2. This defaultconfiguration means that the program stored in the external programmemory (Flash) is executed after a hardware reset. In order to allowthe execution of any code stored in the controller’s on-chip memory,Jumper J1 must be closed at pads 2+3.
The following configurations are possible:
Code Fetch Selection J1from external program memory 1 + 2*from internal program memory 2 + 3
*= Default setting
Table 3: J1 Code Fetch Selection
3.2 J2 Supply Voltage for SRAMs U3/U4
Jumper J2 configures the power supply for the memory deviceinstalled on U3 and U4. The SRAM devices (U3, U4) can beconnected to VCC or VPD using Jumper JP2. The SRAM isconnected to VPD in the default configuration. The VoltageSupervisor Chip (U8) generates VPD from VCC if the main supplyvoltage is available. In the absence of VCC, the Voltage SupervisorChip switches VPD to the back-up battery voltage if a battery isconnected to the phyCORE-DS80C390.
The following configurations are possible:
SRAM Power Supply J2SRAMs U4/U5 connected to VPD 1 + 2*
SRAMs U4/U5 connected to VCC 2 + 3
*= Default setting
Table 4: J2 SRAM Supply Voltage Configuration
Jumpers
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3.3 J3, J4, J5 SRAM Configuration
Jumpers J3, J4 and J5 are used to configure the SRAM memoryconfiguration on the phyCORE-DS80C390. These jumper settings areinstalled during production of the subassembly and must not bechanged by the user at any time.
The following configurations are possible:
SRAM Configuration J3 J4 J5SRAM U3 = 128 kByte 1 + 2* 1 + 2*
SRAM U3 = 512 kByte 2 + 3 2 + 3SRAM U4 = 128 kByte 1 + 2*
SRAM U4 = 512 kByte 2 + 3
*= Default setting
Table 5: J3, J4, J5 SRAM Configuration
3.4 J6, J7 /PCE2 and /PCE3 Configuration
Depending on the configuration of Jumpers J6 und J7, the addressdecoder selects if P5.6 and P5.7 are used as port pins or as ChipSelect signals /PCE2 and /PCE3. If these pins are configured as ChipSelect signals /PCE2 and /PCE3, the address decoder will includethem into the address decoding scheme for the control signals/CS_RAM1 and /CS_RAM2. If P5.6 and P5.7 are configured as portpins, the address decoder will ignore them.
Note:Malfunction or destruction of the phyCORE module can occur if portsP5.6 and P5.7 are configured as port pin in the application programbut are set for use as /PCE2 and /PCE3 Chip Select signal withJumpers J6 and J7.
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The following configurations are possible:
P5.6 and P5.7 Configuration J6 J7P5.6 configured as /PCE2 1 + 2*
P5.6 configured as port pin 2 + 3P5.7 configured as /PCE3 1 + 2*
P5.7 configured as port pin 2 + 3
*= Default setting
Table 6: J6, J7 /PCE2 and /PCE3 Configuration
3.5 J8, J9, J10 Serial Interface Configuration
Jumpers J8, J9 and J10 connect the serial interface signal of thecontroller with either the on-board RS-232 (U10) or the RS-485transceiver (U11).
The following configurations are possible:
Serial Interface J8 J9 J10Serial interface available as RS-232 1 + 2* 1 + 2*
Serial interface available as RS-485 2 + 3 2 + 3RS-485 transceiver is activated via
port P3.51 + 2*
RS-485 transceiver is always active 2 + 3RS-485 transceiver is disabled open
*= Default setting
Table 7: J8, J9, J10 Serial Interface Configuration
Jumpers
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3.6 J13 Interrupt Output of the RTC
Jumper J13 determines if the interrupt output of the RTC (U6)connects to port 3.2 (/INT0). Alternatively, this port pin can be usedas standard I/O signals at pin X1C1 of the phyCORE-connector. Thisrequires opening Jumper J13.
The following configurations are possible:
RTC Interrupt Output J13RTC interrupt output is connected to
port 3.2 (/INT0)closed*
P3.2 available as port pin, RTC interruptoutput not used
open
*= Default setting
Table 8: J13 RTC Interrupt Configuration
3.7 J14, J15 I2C Bus Configuration
Two I²C interface devices - a Real-Time Clock (RTC) at U6 and aserial EEPROM at U7- are available on the phyCORE-DS80C390.These devices are connected via Jumpers J14 (SCL) and J15 (SDA) toport pins P4.2 and P4.3. Use of these pins as standard I/O requiresopening the corresponding jumpers. In this case, the I²C signals mustbe supplied by an external source connected to pins X1F11 (SCL) andX1F12 (SDA) at the phyCORE-connector X1. Refer to section 7 andsection 8 for details on the I²C interface devices.
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The following configurations are possible:
I²C Bus Configuration J14 J15Port P4.2 used as I²C SCL closed*
Port P4.2 used as port pin, I²C SCLexternal via pin X1F11
open
Port P4.3 used as I²C SDA closed*Port P4.3 used as port pin, I²C SDA
external via pin X1F12open
*= Default setting
Table 9: J14, J15 I²C Bus Configuration
3.8 J18, J19, J20, J21 First CAN Interface Configuration
The DS80C390 microcontroller features two on-chip CAN interfaces.The signals for the first CAN interface CAN0 are configured withJumpers J18, J19, J20 and J21. Jumpers J18 (P5.0/C0Tx) andJ19 (P5.1/C0Rx) connect the corresponding microcontroller port pinswith the TxDC and RxDC inputs on the CAN transceiver U13.Jumpers J20 (CANH0/P5.1) and J21 (CANL0/P5.0) route either theCAN transceiver output signal or the applicable microcontroller portpins to the phyCORE-connector pins X1D15 and X1D14.
The following configurations are possible:
CAN0 Configuration J18 J19 J20 J21CANH0 at X1D15 closed* 1 + 2*
P5.1 (C0Tx) at X1D15 open 2 + 3CANL0 at X1D14 closed* 1 + 2*
P5.0 (C0Rx) at X1D14 open 2 + 3
*= Default setting
Table 10: J18, J19, J20 and J21 CAN0 Interface Configuration
Jumpers
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3.9 J11, J12, J16, J17 Second CAN InterfaceConfiguration
The signals for the second CAN interface CAN1 are configured withJumpers J11, J12, J16 and J17. Jumpers J16 (C1Tx/TxD1) andJ17 (C1Rx/RxD1) connect the corresponding microcontroller portpins P5.2 and P5.3 with the TxDC and RxDC inputs on the CANtransceiver U12. Jumpers J11 (CANH1/P5.3) and J12 (CANL1/P5.2)route either the CAN transceiver output signal or the applicablemicrocontroller port pins to the phyCORE-connector pins X1D13 andX1D12.
The following configurations are possible:
CAN1 Configuration J16 J17 J11 J12CANH1 at X1D13 closed* 1 + 2*
P5.3 (C1Tx) at X1D13 open 2 + 3CANL1 at X1D12 closed* 1 + 2*
P5.2 (C1Rx) at X1D12 open 2 + 3
*= Default settings
Table 11: J11, J12, J16 and J17 CAN1 Interface Configuration
3.10 J22 RTC Clockout
Jumper J22 configures the RTC clockout signal. The RTC clockoutsignal remains inactive if J22 is closed at position 1+2. ClosingJumper J22 at position 2+3 activates the RTC clockout signal. Formore information on the RTC clockout signal please refer to the ac-companying RTC Data Sheet.
The following configurations are possible:
RTC Clockout Configuration J22RTC clockout signal is not active 1 + 2*
RTC clockout signal is active 2 + 3
*= Default settings
Table 12: J22 RTC Clockout Configuration
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Memory Models
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4 Memory Models
The Dallas DS80C390 microcontroller features a user configurableChip Select unit which can be configured by software to differentmemory models. An additional address decoder chip is integrated onthe phyCORE-DS80C390. The address decoder generates the I/OChip Select signals, configures the programming model and the vonNeuman memory model.
A hardware reset without active boot condition activates a defaultmemory configuration that is suitable for a variety of applications.However, this memory model can be changed or adjusted at thebeginning of a particular application. In contrast, if the boot conditionis active during hardware reset, the programming model is started. Inthis case the microcontroller firmware, resident in the upper 32 kByteFlash sector, is exectued and allows communication with the PC-sideFlashTools software over an RS-232 connection.
Configuration of the memory models is done within themicrocontroller and address decoder by means of internal controlregisters. Default settings for the Chip Select signals on themicrocontroller are used (/CE0, /CE1 and /PCE0-/PCE3 with1 MByte address space each). The controller can be operated inX4 mode (40 MHz) if the Runtime model is configured. When usingthe Programming model or the von Neumann model the X2 mode(20 MHz) can be selected for the maximum operating frequency.
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The following figure illustrates the Runtime memory model:
Figure 9: Runtime Memory Model Following a Hardware Reset (Boot notActive)
The runtime memory model boasts a Harvard architecture with up to2 MByte Flash and 1 MByte SRAM. The Flash is selected with theChip Select signals /CE0 (0H-FFFFFH) and /CE1(100000H-1FFFFFH). If the capacity of the Flash device is less than1 MByte, it is mirrored (depending on its size) repeatedly in the lower1 MByte memory area. It is important to note that the upper 32 kBytesof Flash contain the FlashTools firmware. This memory area istherefor no longer avialable to the application program. The ChipSelect /PCE0 selects both SRAMs U3/U4, whereby a maximummemory range of 1 MByte can be addressed. If the SRAM capacity isless than 1 MByte, then its contents (depending on memory size) willbe mirrored repeatedly in the 1 MByte memory area for /PCE0. Theaddress decoder is controlled by the Chip Select signal /PCE1. Theaddress decoder generates in turn the 3 I/O Chip Select signals /CS1through /CS3. The Chip Select signals /PCE2 and /PCE3 are availableexternally.
0 8 0 0 0 0 H
1 4 0 0 0 0 H
2 0 0 0 0 0 H
1 C 0 0 0 0 H
1 8 0 0 0 0 H
3 F F F F F H
1 0 0 0 0 0 H
0 C 0 0 0 0 H
0 4 0 0 0 0 H
0 0 0 0 0 0 H
C O D E D A T A
M e m o r y D S 8 0 C 3 9 0
n o t u s e d( / C E 2 )( / C E 3 )
2 M B F L A S H
1 M B F L A S H
5 1 2 k B F L A S H
2 5 6 k B F L A S H
F l a s h T o o l s - F i r m w a r e 3 2 k B
/ C E 1
/ C E 0
/ C E 0
/ C E 0
F l a s h U 5 ( / C E 0 a n d / C E 1 ) S R A M U 3 / U 4 ( / P C E 0 )
/ P C E 2 ( e x t e r n a l )
/ P C E 1
/ P C E 3 ( e x t e r n a l )
/ P C E 0
/ P C E 0
/ P C E 0
/ P C E 0
/ C S 3
/ C S 2
/ C S 1
A D D R . -D E C O D E R
1 2 8 k B S R A M
2 5 6 k B S R A M
5 1 2 k B S R A M
1 M B S R A M
Memory Models
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The following figure illustrates the von Neumann memory model:
Figure 10: Von Neumann Memory Model
The von Neumann model configures a memory area, in which theseperation between CODE and XDATA access is no longer present.This means that both access modes target the same physical memorydevice, usually a RAM device. Von Neuman memory areas areespecially useful if program code needs to loaded and subsequentlyexecuted during runtime (in monitor applications, for example). Inmonitor mode the application program must be executed in SRAMbecause only then is it possible to change machine commands in theCODE area while the program is being executed. This can be usefulin setting a breakpoint within the application program.
0 8 0 0 0 0 H
1 4 0 0 0 0 H
2 0 0 0 0 0 H
1 C 0 0 0 0 H
1 8 0 0 0 0 H
3 F F F F F H
1 0 0 0 0 0 H
0 C 0 0 0 0 H
0 4 0 0 0 0 H
0 0 0 0 0 0 H
C O D E D A T A
M e m o r y D S 8 0 C 3 9 0
n o t u s e d( / C E 2 )( / C E 3 )
2 M B F L A S H
1 M B F L A S H
5 1 2 k B F L A S H
2 5 6 k B F L A S H
F l a s h T o o l s - F i r m w a r e 3 2 k B
F l a s h U 5 ( / C E 0 a n d / C E 1 ) S R A M U 3 / U 4 ( / P C E 0 )
/ P C E 2 ( e x t e r n a l )
/ P C E 1
/ P C E 3 ( e x t e r n a l )
/ P C E 0
/ P C E 0
/ P C E 0
/ P C E 0
/ C S 3
/ C S 2
/ C S 1
A D D R . -D E C O D E R
1 2 8 k B S R A M
2 5 6 k B S R A M
5 1 2 k B S R A M
1 M B S R A M
F A 2 0 = 0
F A 2 0 = 1
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The following steps are necessary to configure the SRAM as vonNeumann:
The program code is stored in the Flash and a routine copies thecontents of the CODE area 1:1 in to the SRAM after a Reset. Next thevon Neumann enable bit is set in the address decoder (ControlRegister 2, bit 0). The program now runs from the SRAM rather thanfrom Flash. It is important to make sure that only a maximum of1 MByte of memory is available for code and data.
The von Neumann memory model can also be used to write to theFlash memory during runtime. If the von Neumann enable bit is set,both Flash areas in the CODE area 100000H-1FFFFFH can beselected using bit FA20 (Control Register 3, bit 0). If FA20 is equal to"0", then the first Megabyte of Flash is accessible, if FA20 is equal to"1", the second Megabyte of Flash is accessible. The controller’s ChipSelect unit supports write and read access to the Flash (see DS80C390Data Sheet), making Flash programming possible.
Memory Models
PHYTEC Meßtechnik GmbH 2002 L-594e_1 29
The following figure illustrates the Programming model:
Figure 11: Programming Model Following a Hardware Reset (Boot Active)
The programming memory model is required in order to start theFlashTools firmware on the module and furthermore initiate serialcommunication with the PC. If the Boot input is active (high) during aReset, the upper 32 kByte block of the Flash is mirrored 64 times inthe controller’s CODE space. The FlashTools firmware is executedbeginning at address 000000H. In this memory model the MUX-Enable bit is set (Control Register 1, bit 0). After the bit is set back tolow ("0"), the user is once again in the runtime memory model. If theFlash is to be programmed, the firmware copies itself into the SRAMand uses the von Neumann memory model to read from and write tothe Flash (see also von Neumann Memory Model).
0 8 0 0 0 0 H
1 4 0 0 0 0 H
2 0 0 0 0 0 H
1 C 0 0 0 0 H
1 8 0 0 0 0 H
3 F F F F F H
1 0 0 0 0 0 H
0 C 0 0 0 0 H
0 4 0 0 0 0 H
0 0 0 0 0 0 H
C O D E D A T A
M e m o r y D S 8 0 C 3 9 0
n o t u s e d( / C E 2 )( / C E 3 )
2 M B F L A S H
1 M B F L A S H
5 1 2 k B F L A S H
2 5 6 k B F L A S H
F l a s h T o o l s - F i r m w a r e 3 2 k B
F l a s h U 5 ( / C E 0 a n d / C E 1 ) S R A M U 3 / U 4 ( / P C E 0 )
/ P C E 2 ( e x t e r n a l )
/ P C E 1
/ P C E 3 ( e x t e r n a l )
/ P C E 0
/ P C E 0
/ P C E 0
/ P C E 0
/ C S 3
/ C S 2
/ C S 1
A D D R . -D E C O D E R
1 2 8 k B S R A M
2 5 6 k B S R A M
5 1 2 k B S R A M
1 M B S R A M
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4.1 Address Decoder Control Registers
Three internal registers are available on the address decoder:
Control Register 1 at address 100000HBit 7 Bit 0Res. 1 Res. Res. Res. Res. Res. BOOT MUX_ENA
Runtime Value:Reset Value:
xxxx xxx0 bxxxx xxxx b
Table 13: Control Register 1 of the Address Decoder
MUX_ENA: The register bit MUX_ENA is set to high duringreset, if a high level signal is applied to the Bootinput of the phyCORE-DS80C390. If the Bootinput stays low during reset, then MUX_ENAremains unchanged.When MUX_ENA is active the upper Flashaddresses FA15 to FA20 are preset to a high signallevel, so that the upper 32 kBytes of Flash aremirrored 64 times in the 2 MByte address areafrom /CE0 - /CE1. In this 32 kByte block theFlashTools firmware for communication with thecorresponding PC software is located. The registercan be read as well as written to.
BOOT: The register BOOT has read-only attributes. If theBoot input is set to high, then a "1" is returned,otherwise a "0".
1: Reserved bits are not to be changed, the default value (0) must remain.
Memory Models
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Control Register 2 at address 100800HBit 7 Bit 0Res. 1 Res. Res. Res. Res. Res. Res. VN_ENA
Runtime Value:Reset Value:
xxxx xxx0 bxxxx xxx0 b
Table 14: Control Register 2 of the Address Decoder
VN_ENA: The register bit VN_ENA is used to configure thevon Neumann memory model. The register can beread as well as written to.
Control Register 3 at address 101000HBit 7 Bit 0Res. 2 Res. Res. Res. Res. Res. HS_DIS FA20
Runtime Value:Reset Value:
xxxx xx00 bxxxx xx00 b
Table 15: Control Register 3 of the Address Decoder
FA20: The register bit FA20 controls the address FA20 ofa 2 MByte Flash device in the von Neumannmemory model. The first megabyte is mapped intothe address range 100000H-1FFFFFH from /CE1 ifthe bit is set to "0". The second megabyte of Flashis mapped to this address range if the bit is set to"1".
HS_DIS: The register bit HS_EN controls the access modeof the SRAM and the Flash device. If HS_DIS = 0then memory is accessed in high-speed mode,enabling the controller to operate in X4 mode. Inthe programming model it is important that the bitHS_DIS = 1, because in this mode the Chip Selectsignals are always seperately active. X2 mode isthe fastest possible mode that the controller canoperate in if HS_DIS = 1.
1: Reserved bits are not to be changed, the default value (0) must remain.2: Reserved bits are not to be changed, the default value (0) must remain.
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Serial Interfaces
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5 Serial Interfaces
5.1 RS-232 Interface
An RS-232 transceiver is located on the phyCORE-DS80C390 atU10. This device adjusts the signal levels of the P3.0/RxD0 andP3.1/TxD0 lines. The RS-232 interface enables connection of themodule to a COM port on a host-PC. In this instance, the RxD0 line(X1F15) of the transceiver is connected to the TxD line of the COMport; while the TxD0 line (X1F14) is connected to the RxD line of theCOM port. The Ground potential of the phyCORE-DS80C390circuitry needs to be connected to the applicable ground pin on theCOM port as well.
The microcontroller’s on-chip UART does not support handshakesignal communication. However, depending on user needs, handshakecommunication can be software emulated using port pins on themicrocontroller. Use of an RS-232 signal level in support ofhandshake communication requires use of an external RS-232transceiver not located on the module.
5.2 RS-485 Interface
As an option to the RS-232 interface, a RS-485 interface can beconfigured on the phyCORE-DS80C390 using the lines P3.0/RxD0and P3.1/TxD0. Jumpers J8 and J9 enable selection between RS-232and RS-485 interfaces (see section 3.5).
The RS-485 transceiver (U11) supports up to 32 nodes in one bussystem. Data transmission occurs via differential signal levelsaccording to RS-485 interface standards.
Note:To utilize the RS-485 interface, Jumper J10 must be closed with a0 Ω / 0805-shape resistor. Setting Jumper J10 to position 1+2 enablescontrol of the transmit function on the RS-485 transceiver IC viaport 3.5. Setting J10 to position 2+3 always activates the RS-485transceiver (refer to section 3.5).
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5.3 CAN Interface
Two CAN transceivers are populated at U12 and U13 on thephyCORE-DS80C390 module. These transceivers enabletransmission and receipt of CAN signals via C0Tx/C0Rx andC1Tx/C1Rx, respectively. Each CAN transceiver supports up to110 nodes on a single CAN bus. Data transmission occurs withdifferential signals between CANH and CANL. A Ground connectionbetween nodes on a CAN bus is not required, yet is recommended tobetter protect the network from electromagnetic interference (EMI).In order to ensure proper message transmission via the CAN bus, a120 Ohm terminating resistor must be connected to each end of theCAN bus between the pins delivering the CANH and CANL signals.
For larger CAN networks, an external opto-coupler should beimplemented to galvanically separate the CAN bus signals and thephyCORE-DS80C390 circuitry. This requires that the C0Tx, C0Rx,C1Tx and C0Rx lines be separated from the on-board CANtransceiver by opening Jumpers J16 through J19. In addition JumpersJ11, J12, J20 and J21 must all be configured to position 2+3. (refer tosections 3.8 and 3.9). The Hewlett Packard HCPL06xx or ToshibaTLP113 HCPL06xx fast opto-coupler is recommended. Parametersfor configuring a proper CAN bus system are found in the DS102norms from the CiA1 (CAN in Automation) User and Manufacturer’sInterest Group.
_______________________1: CiA CAN in Automation – International User‘s and Manufacturer’s Union, founded in March
1992. CiA offers technical, product- and market-related information on the topic of ControllerArea Network, with the goal of increasing general knowledge about CAN and furthering futuredevelopment of the CAN protocol.
Flash Memory
PHYTEC Meßtechnik GmbH 2002 L-594e_1 35
6 Flash Memory (U5)
Flash, as non-volatile memory on the phyCORE-DS80C390, providesan easily reprogrammable means of code storage to the user. Thefollowing tables gives an overview on available Flash types that canpopulkate the phyCORE module.
Type Capacity Manufacturer Device Code ManufacturingCode
29F200T 256 kByte AMD 2251 0129F200T 256 kByte Fujitsu 2251 0429F400T 512 kByte AMD 2223 0129F400T 512 kByte Fujitsu 2223 0429F800T 1 MByte AMD 22D6 0129F800T 1 MByte Fujitsu 22D6 0429F160T 2 MByte AMD 22D2 0129F160T 2 MByte Fujitsu 22D2 04
Table 16: Flash Memory and Manufacturer Overview
Flash memory devices offer up to 100,000 reprogramming cycles, andenable on-board programming of user code. These Flash devices areprogrammable with 5 V. No dedicated programming voltage isrequired. All standard versions of the phyCORE-DS80C390 feature aprogramming utility firmware – FlashTools (refer to applicableQuickStart Instruction for more details) – resident in the Flashdevice.
This firmware enables on-board download, as well as subsequenterasure and reprogramming, of user code into the Flash with the helpof an intuitive PC-side software. The FlashTools firmware portionresides in the upper 32 kByte of Flash memory, which is not availablefor storage of user code. The total memory available for userprograms depends on the mounted memory device (refer toFigure 12).
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Note:Should the FlashTools firmware portion be erased from the Flashdevice without having a back-up or an equivalent replacement,reprogramming is no longer possible!
Please note that this firmware protects itself against any intentional oraccidental erasure or overwriting. As the Flash device’s hardwareprotection mechanism is not utilized, protection is limited to thesoftware level. In the event that a user wishes to download his or herown programming algorithms or tools into the Flash, the user mustensure that a programming tool remains in the Flash memory. Refer tothe “QuickStart Instructions" for a detailed description of theon-board programming procedure.
Figure 12: Memory Areas of the Flash Device
00000H
3FFFFH
29F200
29F160
FlashTools firmware(software protected)
256kByte 256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
256kByte
29F400
29F800
32kB
Flash Memory
PHYTEC Meßtechnik GmbH 2002 L-594e_1 37
Use of a Flash device as the only code memory results in limitedusability of the Flash as non-volatile memory for data. This is due tothe internal structure of the Flash device as, during the Flash’sinternal programming process, the reading of data from Flash is notpossible. For Flash programming, program execution must betransferred out of Flash (such as into von Neumann RAM). Thisusually equals the interruption of a "normal" program execution cycle.
As of the printing of this manual, Flash devices generally have a lifeexpectancy of at least 100,000 erase/program cycles.
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7 Serial EEPROM (U7)
A non-volatile memory with a serial (I²C bus) interface populatesspace U7 on the phyCORE-DS80C390. This device is intended tostore configuration parameters and user data. This memory device canbe in the form of an EEPROM device or an FRAM device. The I²Cbus is generated using port pins P4.2 (SCL) and P4.3 (SDA). Byopening the two solder Jumpers J14 and J15, the I²C bus can bedisconnected from the controller pins. In this case, these pins areavailable as freely available port pins.
In the default configuration, an EEPROM populates space U7. Withapproximately 106 write and erase cycles an EEPROM memorydevice is a reliable solution for most requirements. For applicationsthat require frequent and fast storage of a large amount of data, othermemory devices can be populated on U7. Modern I²C FRAMs withapproximately 1010 write and erase cycles can be used for thispurpose. These ferro-electrical memory devices can store data, even ifno power is supplied to the module.
Addressing Scheme:
The address lines A0 (IC pin 1) and A1 (IC pin 2) are connected toGND. Address line A2 (IC pin 3) is connected to VCC. The addressconfiguration for the memory devices is shown in the table below:
Device Type Capacity Manufacturer / Type AddressEEPROM 4 kByte Catalyst 24WC32 1010100EEPROM 8 kByte Catalyst 24WC64 1010100FRAM 512 Byte Ramtron FM24C04 101010xFRAM 8 kByte Ramtron FM24C64 1010100
Table 17: Memory Device Options at U7
Real-Time Clock RTC-8564
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8 Real-Time Clock RTC-8564 (U6)
For real-time or time-driven applications the phyCORE-DS80C390 isequipped with an RTC-8564 Real-Time Clock (RTC) at U6. ThisRTC device provides the following features:
• serial input/output bus (I2C)• power consumption
bus active: max. 50 mAbus inactive, CLKOUT = 32 kHz : max. 1.7 µAbus inactive, CLKOUT = 0 kHz : max. 0.75 µA
• clock function with four year calendar• century bit for year 2000-compliance• universal timer with alarm and overflow indication• 24-hour format• automatic word address incrementing• programmable alarm, timer and interrupt functions
If the phyCORE-DS80C390 is connected to a battery buffer, theReal-Time Clock runs independently of the module’s power supply.
Programming of the Real-Time Clock is done via the I2C bus(I2C address 1010001), connected to port P4.2 (SCL) and portP4.3 (SDA) on the controller. The Real-Time Clock also provides aninterrupt output which extends to port P3.2 via Jumper J13. Aninterrupt occurs in case of a clock alarm, timer alarm, timer overflowand event counter alarm. All interrupts must then be cleared bysoftware. With the interrupt function the Real-Time Clock can beutilized in various applications. For more information on the featuresof the RTC-8564, refer to the corresponding Data Sheet located onthe Spectrum CD.
Note:Following attachment of a power supply to the board, the RTCgenerates no interrupts, as the RTC is not yet initialized.
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9 Reset Controller (U8)
The Reset Controller at U8 is used to generate a definite release of theReset signal if the supply voltage VCC drops below 4.65 V. Thisensures the proper start-up of the microcontroller. Furthermore, theReset Controller can switch the voltage of a back-up battery as VPDto several IC’s in case the main power supply becomes interrupted.The basic characteristics of this IC are described in the appropriateData Sheet, which is available on the Spectrum CD.
All pins of the Reset Controller are routed to the phyCORE-connector. The VPD voltage is available on the OUT pin of the ResetController. In normal operation mode this pin is supplied by VCC (viaa diode). Additionally, VBAT is routed via the voltage dividerR19/R20 to pin PFI. If VBAT = 3.3 V, a voltage of 1.65 V isavailable at PFI. If the voltage at PFI drops below 1.25 V, the signal/PFO is released. The signals WDI and /PFO are available at thephyCORE-connector pins X1D5 and X1F5.
Remote Supervisor Chip
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10 Remote Supervisory Chip (U9)
Space U9 is intended to be populated by an RSC1308 RemoteSupervisory Chip. This IC can initiate a boot sequence via a serialinterface, such as RS-232 or RS-485. The RSC can start PHYTECFlashTools without requiring a manual reset of the phyCORE modulevia a Boot jumper or button. This enables a remote software update ofthe on-board Flash device.
This feature will be available on future phyCORE modules.
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11 Battery Buffer
The battery that buffers the memory is not essential to the functioningof the phyCORE-DS80C390. However, this battery buffer embodiesan economical and practical means of storing nonvolatile data inSRAM and is necessary for data storage in the Real-Time Clock incase of a power failure.
The VBAT input at pin X1D4 of the module is provided forconnecting the external battery. The negative polarity pin on thebattery must be connected to GND on thephyCORE-DS80C390. As of the printing of this manual, a lithiumbattery is recommended as it offers relatively high capacity at lowdischarge. In the event of a power failure at VCC, the SRAM memory(U3/U4) and the RTC (U6) will be buffered by a battery connected toVBAT.
Power consumption depends on the installed components and memorysize. Refer to the corresponding Data Sheets for the SRAM devicesmounted on the phyCORE module (refer also to section 12,“Technical Specifications”).
Note:Be advised that despite the battery buffer, changes in the data contentwithin the RAM can occur. The battery buffer does not completelyremove the danger of data destruction.
Technical Specifications
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12 Technical Specifications
The physical dimensions of the phyCORE-DS80C390 are representedin Figure 13. The module’s profile (not including the pin headerconnectors) is approximately 11 mm thick, with a maximumcomponent height of 3.5 mm on the back-side of the PCB andapproximately 6 mm on the front-side. The PCB itself isapproximately 1.5 mm thick.
Figure 13: Physical Dimensions (not Shown at Scale)
a
a
a = 2.10 mm
55.00 mm
47.50 mm
b
b
b = 2.54 mm
38.10 mm
b
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Additional specifications:
• Dimensions: 55 x 47.5 mm, ±0.01 mm• Weight: approximately 25 g with all optional
components mounted on the module• Storage temperature: -40°C to +90°C• Operating temperature: standard 0°C to +70°C,
extended -40°C to +85°C• Humidity: maximum 95 % r.F. not condensed• Operating voltage: 5 V ±5 %,• VBAT: 3 V ±10 %,• Power consumption: maximum 220 mA, typically 110 mA
at 10 MHz oscillator frequency and128 kByte RAM at +20°C
• Power consumptionwith battery buffer: maximum 100 µA,
typically 1 µA for RAM supply and1 µA for Real-Time Clock supplyat +20°C
• Delay Time /CS1- /CS3: 10 ns
These specifications describe the standard configuration of thephyCORE-DS80C390 as of the printing of this manual.
Please note that the module storage temperature is only 0°C to +70°Cif a battery buffer is used for the RAM devices.
Hints for Handling the Module
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13 Hints for Handling the Module
Removal of the standard quartz or oscillator is not advisable given thecompact nature of the module. Should this nonetheless be necessary,please ensure that the board, as well as surrounding components andsockets, remain undamaged while desoldering. Overheating the boardcan cause the solder pads to loosen, rendering the module inoperable.Carefully heat neighboring connections in pairs. After a few alterna-tions, components can be removed with the solder-iron tip. Alterna-tively, a hot air gun can be used to heat and loosen the bonds.
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The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 47
14 The phyCORE-DS80C390 on the phyCOREDevelopment Board LD 5V
PHYTEC Development Boards are fully equipped with all mechanicaland electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicablePHYTEC Single Board Computer (SBC) modules. DevelopmentBoards are designed for evaluation, testing and prototyping ofPHYTEC Single Board Computers in labratory environments prior totheir use in customer designed applications.
14.1 Concept of the phyCORE Development Board LD 5V
The phyCORE Development Board LD 5V provides a flexibledevelopment platform enabling quick and easy start-up andsubsequent programming of the phyCORE-DS80C390 Single BoardComputer module. The Development Board design allows easy con-nection of additional expansion boards featuring various functionsthat support fast and convenient prototyping and software evaluation.
This modular development platform concept is depicted in Figure 14and includes the following components:
• The actual Development Board (1), which offers all essentialcomponents and connectors for start-up including: a power socketenabling connection to an external power adapter (2) and serialinterfaces (3) of the SBC module at DB-9 connectors (dependingon the module, up to two RS-232 interfaces and up to two RS-485or CAN interfaces).
• All of the signals from the SBC module mounted on theDevelopment Board extend to two mating receptacle connectors.A strict 1:1 signal assignment is consequently maintained from thephyCORE-connectors on the module to these expansion con-nectors. Accordingly, the pin assignment of the expansion bus (4)depends entirely on the pinout of the SBC module mounted on theDevelopment Board.
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• As the physical layout of the expansion bus is standardized acrossall applicable PHYTEC Development Boards, PHYTEC is able tooffer various expansion boards (5) that attach to the DevelopmentBoard at the expansion bus connectors. These modular expansionboards offer supplemental I/O functions (6) as well as peripheralsupport devices for specific functions offered by the controllerpopulating the SBC module (9) mounted on the DevelopmentBoard.
• All controller and on-board signals provided by the SBC modulemounted on the Development Board are broken out 1:1 to theexpansion board by means of its patch field (7). The requiredconnections between SBC module / Development Board and theexpansion board are made using patch cables (8) included withthe expansion board.
The following figure illustrates the modular development platformconcept:
Figure 14: Modular Development and Expansion Board Concept with thephyCORE-DS80C390
The following sections contain specific information relevant to theoperation of the phyCORE-DS80C390 mounted on the phyCOREDevelopment Board LD 5V. For a general description of theDevelopment Board, please refer to the corresponding DevelopmentBoard Hardware Manual.
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 49
14.2 Development Board LD 5V Connectors and Jumpers
14.2.1 Connectors
As shown in Figure 15, the following connectors are available on thephyCORE Development Board LD 5V:
X1- low-voltage socket for power supply connectivityX2- mating receptacle for expansion board connectivityP1- dual DB-9 sockets for serial RS-232 interface connectivityP2- dual DB-9 connectors for CAN or RS-485 interface
connectivityX4- voltage supply for external devices and subassembliesX5- GND connector (for connection of GND signal of measuring
devices such as an oscilliscope)X6- phyCORE-connector enabling mounting of applicable
phyCORE modulesBAT1- receptacle for an optional battery
Figure 15: Location of Connectors on the phyCORE Development Board LD 5V
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Please note that all module connections are not to exceed theirexpressed maximum voltage or current. Maximum signal input valuesare indicated in the corresponding controller User’s Manual/DataSheets. As damage from improper connections varies according to useand application, it is the user's responsibility to take appropriatesafety measures to ensure that the module connections are protectedfrom overloading through connected peripherals.
14.2.2 Jumpers on the phyCORE Development Board LD 5V
Peripheral components of the phyCORE Development Board LD 5Vcan be connected to the signals of the phyCORE-DS80C390 bysetting the applicable jumpers.
The Development Board’s peripheral components are configured foruse with the phyCORE-DS80C390 by means of insertable jumpers. Ifno jumpers are set, no signals connect to the DB-9 connectors, thecontrol and display units and the CAN transceivers. The Reset inputon the phyCORE-DS80C390 directly connects to the Resetbutton (S2). Figure 16 illustrates the numbering of the jumper pads,while Figure 17 indicates the location of the jumpers on theDevelopment Board.
Figure 16: Numbering of Jumper Pads
e.g.: JP28 e.g.: JP23 e.g.: JP24
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 51
Figure 17: Location of the Jumpers (View of the Component Side)
Figure 18 shows the factory default jumper settings for operation ofthe phyCORE Development Board LD 5V with the standardphyCORE-DS80C390 (standard = DS80C390 controller, use of thefirst RS-232 interface, two CAN interfaces, LED D3, the Boot buttonon the Development Board). Jumper settings for other functionalconfigurations of the phyCORE-DS80C390 module mounted on theDevelopment Board are described in section 14.3.
Figure 18: Default Jumper Settings of the phyCORE Development Board LD 5Vwith phyCORE-DS80C390
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14.2.3 Unsupported Features and Improper Jumper Settings
The following table contains improper jumper settings for operationof the phyCORE-DS80C390 on a phyCORE DevelopmentBoard LD 5V. Functions configured by these settings are notsupported by the phyCORE module.
Supply Voltage:
The phyCORE Development Board LD 5V supports two main supplyvoltages for the start-up of various phyCORE modules. When usingthe phyCORE-DS80C390, only one main supply voltage is required,VCC1 with 5 V. The connector pins for a second supply voltage onthe phyCORE-DS80C390 are not defined.
Sockets G and H on the phyCORE Development Board LD 5Vsupport connection of supply voltages for analog components. ThephyCORE-DS80C390 is not populated with these sockets, andtherefore Jumpers J36 to J38 must remain open.
Jumper Setting DescriptionJP16 closed VCC2 routed to phyCORE-DS80C390JP36 closed AVDD routed to phyCORE-DS80C390JP37 closed REF+ routed to phyCORE-DS80C390JP38 closed REF- routed to phyCORE-DS80C390
Table 18: Improper Jumper Settings for the Development Board
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 53
14.3 Functional Components on the phyCOREDevelopment Board LD 5V
This section describes the functional components of the phyCOREDevelopment Board LD 5V supported by thephyCORE-DS80C390 and appropriate jumper settings to activatethese components. Depending on the specific configuration of thephyCORE-DS80C390 module, alternative jumper settings can beused. These jumper settings are different from the factory defaultsettings as shown in Figure 18 and enable alternative or additionalfunctions on the phyCORE Development Board LD 5V depending onuser needs.
14.3.1 Power Supply at X1
Caution:Do not use a laboratory adapter to supply power to the DevelopmentBoard! Power spikes during power-on could destroy the phyCOREmodule mounted on the Development Board! Do not change modulesor jumper settings while the Development Board is supplied withpower!
Permissible input voltage: +/-5 VDC regulated.
The required current load capacity of the power supply depends onthe specific configuration of the phyCORE-DS80C390 mounted onthe Development Board as well as whether an optional expansionboard is connected to the Development Board. An adapter with aminimum supply of 500 mA is recommended.
Jumper Setting DescriptionJP9 2 + 3 5 V main supply voltage
to the phyCORE-DS80C390
Table 19: JP9 Configuration of the Main Supply Voltage VCCI
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Figure 19: Connecting the Supply Voltage at X1
Caution:When using this function, the following jumper settings are notallowed:
Jumper Setting DescriptionJP9 1 + 2 3.3 V as main supply voltage
for the phyCORE-DS80C390open phyCORE-DS80C390 not connected to
main supply voltage
Table 20: JP9 Improper Jumper Settings for the Main Supply Voltage
Setting Jumper JP9 to positions 1+2 configures a main power supplyto the phyCORE-DS80C390 of 3.3 V which could destroy themodule. If Jumper JP9 is open, no main power supply is connected tothe phyCORE-DS80C390. This jumper setting should therefore not beused.
+5 VDC
GND
≥ 500 mA
Center Hole1.3 mm 3.5 mm
-- +Polarity:
The phyCORE-DS80C390 on the phyCORE Development Board
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14.3.2 Starting FlashTools
The Flash memory of the phyCORE-DS80C390 contains theFlashTools firmware. The combination of this firmware and thecorresponding software installed on the PC allow for on-board Flashprogramming with application programs via an RS-232 interface.
In order to start the FlashTools on the phyCORE-DS80C390, theBoot pin (X1D6) of the phyCORE module must be connected to ahigh-level signal at the time the Reset signal changes from its activeto the inactive state.
The phyCORE Development Board LD 5V provides three differentoptions to enable the Flash-programming mode:
1. The Boot button (S1) can be connected to VCC via Jumper JP28located next to the Boot and Reset buttons at S1 and S2. Thisconfiguration enables start-up of the FlashTools firmware if theBoot button is pressed during a hardware reset or power-on.
Jumper Setting DescriptionJP28 3 + 4 Boot button (in conjunction with Reset button or
connection of the power supply) starts the FlashToolsfirmware on the phyCORE-DS80C390
Table 21: JP28 Configuration of the Boot Button
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2. The Boot input of the phyCORE-DS80C390 can also be perma-nently connected to VCC. This spares pushing the Boot buttonduring a hardware reset or power-on.
Jumper Setting DescriptionJP28 2 + 4 Boot input connected permanently with VCC.
FlashTools are always started with Reset button orwith connection of the power supply
Table 22: JP28 Configuration of a Permanent FlashTools Start Condition
Caution:In this configuration a regular reset, hence normal start of yourapplication, is not possible. The FlashTools firmware is started everytime. This is useful when using an emulator.
3. It is also possible to start the FlashTools via external signalsapplied to the DB-9 socket P1A. This requires control of the signaltransition on the Reset line (/RESIN) via pin 7 while a static high-level is applied to pin 4 for the Boot signal.
Jumper Setting DescriptionJP22 1 + 2 Pin 7 (CTS) of the DB-9 socket P1A as Reset signal
for the phyCORE-DS80C390JP23 1 + 2 Pin 4 (DSR) of the DB-9 socket P1A as Boot signal
for the phyCORE-DS80C390JP10 2 + 3 High-level Boot signal connected with the Boot input
of the phyCORE-DS80C390
Table 23: JP22, JP23, JP10 Configuration of Boot via RS-232
Caution:When using this function, the following jumper setting is not allowed:
Jumper Setting DescriptionJP10 1 + 2 Jumper setting generates low-level on Boot input
of the phyCORE-DS80C390
Table 24: Improper Jumper Settings for Boot via RS-232
The phyCORE-DS80C390 on the phyCORE Development Board
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14.3.3 First Serial Interface at Socket P1A
Socket P1A is the lower socket of the double DB-9 connector at P1.P1A is connected via jumpers to the first serial interface of thephyCORE-DS80C390. When connected to a host-PC, thephyCORE-DS80C390 can be rendered in FlashTools mode viasignals applied to the socket P1A (refer to section 14.3.2).
Jumper Setting DescriptionJP20 closed 1 Pin 2 of DB-9 socket P1A connected with RS-232
interface signal TxD0 of the phyCORE-DS80C390open Pin 2 of DB-9 socket P1A not connected
JP21 open Pin 9 of DB-9 socket P1A not connectedJP22 open Pin 7 of DB-9 socket P1A not connected
1 + 2 Reset input of the module can be controlled viaRTS signal from a host-PC
JP23 open Pin 4 of DB-9 socket P1A not connected1 + 2 Boot input of the module can be controlled via
DTR signal from a host-PCJP24 open Pin 6 of DB-9 socket P1A not connectedJP25 open Pin 8 of DB-9 socket P1A not connectedJP26 open Pin 1 of DB-9 socket P1A not connectedJP27 closed 1 Pin 3 of DB-9 socket P1A connected with RS-232
interface signal RxD0 from the phyCORE-DS80C390open Pin 3 of DB-9 socket P1A not connected
1 = required for communication with FlashTools
Table 25: Jumper Configuration for the RS-232 Interface
Pin 2: TxD0
Pin 3: RxD0
Pin 5: GND
Figure 20: Pin Assignment of the DB-9 Socket P1A as RS-232 (Front View)
1
2
3
4
7
6
5
8
9
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14.3.4 Socket P1B
Socket P1B is the upper socket of the double DB-9 connector at P1.The phyCORE-DS80C390 does not support a second RS-232interface. Socket P1B remains unused.
Jumper Setting DescriptionJP1 open Pin 2 of the DB-9 socket P1B not connectedJP2 open Pin 9 of the DB-9 socket P1B not connectedJP3 open Pin 7 of the DB-9 socket P1B not connectedJP4 open Pin 4 of the DB-9 socket P1B not connectedJP5 open Pin 6 of the DB-9 socket P1B not connectedJP6 open Pin 8 of the DB-9 socket P1B not connectedJP7 open Pin 1 of the DB-9 socket P1B not connectedJP8 open Pin 3 of the DB-9 socket P1B not connectedJP40 open Pin 2 of the DB-9 socket P1B not connectedJP41 open Pin 3 of the DB-9 socket P1B not connected
Table 26: Jumper Configuration of the DB-9 Socket P1B
Figure 21: Pin Assignment of the DB-9 Socket P1B (Front View)
1
2
3
4
7
6
5
8
9
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 59
Caution:When using the phyCORE-DS80C390 mounted on a phyCOREDevelopment Board LD 5V the following jumper settings are notfunctional and could damage the module:
Jumper Setting DescriptionJP1 closed Pin 2 of the DB-9 socket P1B is connected to
B (RS-485) of the phyCORE-DS80C390JP3 closed Pin 2 of the DB-9 socket P1B is connected to
A19 of the phyCORE-DS80C390JP6 closed Pin 2 of the DB-9 socket P1B is connected to
port P5.6 (/PCE2) of the phyCORE-DS80C390JP8 closed Pin 3 of the DB-9 socket P1B is connected to
A (RS-485) of the phyCORE-DS80C390JP40 closed Pin 2 of the DB-9 socket P1B is connected to
the SCL signal of the phyCORE-DS80C390JP41 closed Pin 3 of the DB-9 socket P1B is connected to
the SDA signal of the phyCORE-DS80C390
Table 27: Improper Jumper Settings for Configuration of P1B
If an RS-232 cable is connected to P1B by mistake the voltage levelon the RS-232 lines could destroy the phyCORE-DS80C390.
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14.3.5 First CAN Interface at Plug P2A
Plug P2A is the lower plug of the double DB-9 connector at P2. P2Ais connected to the first CAN interface (CAN0) of thephyCORE-DS80C390 via jumpers. Depending on the configurationof the CAN transceivers and their power supply, the following threeconfigurations are possible:
1. CAN transceiver populating the phyCORE-DS80C390 is enabledand the CAN signals from the module extend directly to plug P2A.
Jumper Setting DescriptionJP31 2 + 3 Pin 2 of the DB-9 plug P2A is connected to CAN-L0
from on-board transceiver on the phyCORE moduleJP32 2 + 3 Pin 7 of the DB-9 plug P2A is connected to CAN-H0
from on-board transceiver on the phyCORE moduleJP11 open Input at opto-coupler U4 on the phyCORE
Development Board LD 5V openJP12 open Output at opto-coupler U5 on the phyCORE
Development Board LD 5V openJP13 open No supply voltage to CAN transceiver and opto-coupler
on the phyCORE Development Board LD 5VJP18 open No GND potential at CAN transceiver and opto-coupler
on the phyCORE Development Board LD 5VJP29 open No power supply via CAN busJP42 open Input at opto-coupler U4 on the phyCORE
Development Board LD 5V openJP43 open Output at opto-coupler U5 on the phyCORE
Development Board LD 5V open
Table 28: Jumper Configuration for CAN Plug P2A using the CAN Transceiveron the phyCORE-DS80C390
Pin 3: GND (Development Board Ground)Pin 7: CAN-H0 (not galvanically separated)Pin 2: CAN-L0 (not galvanically separated)Pin 6: GND (Development Board Ground)
Figure 22: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver onphyCORE-DS80C390)
1
2
3
4
7
6
5
8
9
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 61
Caution:When using the DB-9 plug P2A as CAN interface and the CANtransceiver on the phyCORE-DS80C390 the following jumpersettings are not functional and could damage the module:
Jumper Setting DescriptionJP31 1 + 2 Pin 2 of DB-9 plug P2A connected with CAN-L0 from
CAN transceiver on the Development BoardJP32 1 + 2 Pin 7 of DB-9 plug P2A connected with CAN-H0 from
CAN transceiver on the Development Board1 + 2 Input at opto-coupler U4 on the Development Board
connected with CAN-L0/C0Tx from phyCORE moduleJP11
2 + 3 CAN-L1 / C1Tx from phyCORE-DS80C390 isconnected to CAN transceiver U2 via opto-coupler U4
1 + 2 Output at opto-coupler U5 on the Development Boardconnected with CAN-H0/C0Rx on phyCORE module
JP12
2 + 3 CAN-H1 / C0Rx from phyCORE-DS80C390 isconnected to CAN transceiver U2 via opto-coupler U5
1 + 2 Supply voltage for CAN circuitry derived from externalsource (CAN bus) via on-board voltage regulator
JP13
2 + 3 Supply voltage for CAN transceivers and opto-couplersderived from local supply circuitry on the Dev. Board
JP18 closed CAN transceiver and opto-coupler on the DevelopmentBoard connected with local GND potential
JP29 closed Supply voltage for on-board voltage regulatorfrom pin 9 of DB-9 plug P2A
JP42 closed Input on opto-coupler U4 on the Development Board isconnected with P3.5 of the phyCORE-DS80C390
JP43 closed Output at opto-coupler U5 on the Development Boardconnected with P3.4 of the phyCORE-DS80C390
Table 29: Improper Jumper Settings for the CAN Plug P2A (CAN Transceiveron phyCORE-DS80C390)
phyCORE-DS80C390
62 PHYTEC Meßtechnik GmbH 2002 L-594e_1
2. The CAN transceiver U13 populating the phyCORE-DS80C390 isdisabled; CAN signals generated by the CAN transceiver (U2) onthe Development Board extending to connector P2A withoutgalvanic seperation.
Note:The phyCORE-DS80C390 must be configured for external CANtransceiver to support this function (refer section 3.8)!
Jumper Setting DescriptionJP31 1 + 2 Pin 2 of DB-9 plug P2A connected with CAN-L0 from
CAN transceiver U2 on the Development BoardJP32 1 + 2 Pin 7 of DB-9 plug P2A connected with CAN-H0 from
CAN transceiver U2 on the Development BoardJP11 1 + 2 Input at opto-coupler U4 on the Dev. Board connected
to CAN-L0 / C0Tx of the phyCORE-DS80C390JP12 1 + 2 Output at opto-coupler U5 on the Dev. Board connected
to CAN-H0 / C0Rx of the phyCORE-DS80C390JP13 2 + 3 Supply voltage for CAN transceiver and opto-coupler
derived from local supply circuitry on thephyCORE Development Board LD 5V
JP18 closed CAN transceiver and opto-coupler on the DevelopmentBoard connected with local GND potential
JP29 open No power supply via CAN busJP42 open Input at opto-coupler U4 on the Dev. Board not
connected to P3.5 of the phyCORE-DS80C390JP43 open Output at opto-coupler U5 on the Dev. Board not
connected to P3.4 of the phyCORE-DS80C390
Table 30: Jumper Configuration for CAN Plug P2A using the CAN Transceiveron the Development Board
Pin 3: GND (Development Board Ground)Pin 7: CAN-H0 (not galvanically separated)Pin 2: CAN-L0 (not galvanically separated)Pin 6: GND (Development Board Ground
Figure 23: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver onDevelopment Board)
1
2
3
4
7
6
5
8
9
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 63
Caution:When using the DB-9 connector P2A as CAN interface and the CANtransceiver on the Development Board the following jumper settingsare not functional and could damage the module:
Jumper Setting DescriptionJP31 2 + 3 Pin 2 of DB-9 plug P2A connected with CAN-
L0/C0Tx from on-board transceiver on the phyCORE-DS80C390
JP32 2 + 3 Pin 7 of P2A connected with CAN-H0/C0Rx fromon-board transceiver on the phyCORE-DS80C390
JP11 2 + 3 Input at opto-coupler U4 on the Development Boardconnected with CAN-L1/C1Tx from phyCORE module
JP12 2 + 3 Output at opto-coupler U5 on the Development Boardconnected with CAN-H1 /C1Rx on phyCORE module
JP13 1 + 2 Supply voltage for CAN transceiver and opto-coupleron the Development Board derived from externalsource (CAN bus) via on-board voltage regulator
JP29 closed Supply voltage for on-board voltage regulatorfrom pin 9 of DB-9 connector P2A
JP42 closed Input at opto-coupler U4 on the Development Boardconnected to P3.5 of the phyCORE-DS80C390
JP43 closed Output at opto-coupler U5 on the Development Boardconnected to P3.4 of the phyCORE-DS80C390
Table 31: Improper Jumper Settings for the CAN Plug P2A (CAN Transceiveron the Development Board)
phyCORE-DS80C390
64 PHYTEC Meßtechnik GmbH 2002 L-594e_1
3. The CAN transceiver U13 populating the phyCORE-DS80C390 isdisabled; CAN signals generated by the CAN transceiver (U2) onthe Development Board extend to connector P2A with galvanicseparation. This configuration requires connection of an externalCAN supply voltage of 7 to 13 V, 14 to 20 V or 21 to 27 V. Theexternal power supply must be only connected to either P2A orP2B.
Note:The phyCORE-DS80C390 must be configured for external CANtransceiver to support this function (refer section 3.8)!
Jumper Setting DescriptionJP31 1 + 2 Pin 2 of DB-9 plug P2A connected with CAN-L0 from
CAN transceiver U2 on the Development BoardJP32 1 + 2 Pin 7 of DB-9 plug P2A connected with CAN-H0 from
CAN transceiver U2 on the Development BoardJP11 1 + 2 Input at opto-coupler U4 on the Development Board
connected to CAN-L0 / C0Tx of the phyCORE moduleJP12 1 + 2 Output at opto-coupler U5 on the Development Board
connected to CAN-H0 / C0Rx of the phyCORE moduleJP13 1 + 2 Supply voltage for CAN transceiver and opto-coupler
on the Development Board derived from external source(CAN bus) via on-board voltage regulator
JP18 open CAN transceiver and opto-coupler on the DevelopmentBoard disconnected from local GND potential
JP29 closed Supply voltage for on-board voltage regulatorfrom pin 9 of DB-9 plug P2A
1 + 2 external CAN supply of 7 to 13 V2 + 3 external CAN supply of 14 to 20 V
JP39
open external CAN supply of 21 to 27 VJP42 open Input at opto-coupler U4 on the Development Board not
connected to P3.5 of the phyCORE-DS80C390JP43 open Output at opto-coupler U5 on the Development Board
not connected to P3.4 of the phyCORE-DS80C390
Table 32: Jumper Configuration for CAN Plug P2A using the CAN Transceiveron the Development Board with Galvanic Separation
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 65
Pin 9: VCAN+
Pin 3: VCAN-Pin 7: CAN-H0 (galvanically separated)Pin 2: CAN-L0 (galvanically separated)Pin 6: VCAN-
Figure 24: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver onDevelopment Board with Galvanic Separation)
Caution:When using the DB-9 plug P2A as CAN interface and the CANtransceiver on the Development Board with galvanic separation thefollowing jumper settings are not functional and could damage themodule:
Jumper Setting DescriptionJP31 2 + 3 Pin 2 of P2A connected with CAN-L0 / C0Tx from on-
board transceiver on the phyCORE-DS80C390JP32 2 + 3 Pin 7 of P2A connected with CAN- H0 / C0Rx from
on-board transceiver on the phyCORE-DS80C390JP11 2 + 3 Input at opto-coupler U4 on the Development Board
connected with CAN-L1/C1Tx from phyCORE moduleJP12 2 + 3 Output at opto-coupler U5 on the Development Board
connected with CAN-H1 /C1Rx on phyCORE moduleJP13 2 + 3 Supply voltage for CAN transceiver and opto-coupler
derived from local supply circuitry on thephyCORE Development Board LD 5V
JP18 closed CAN transceiver and opto-coupler on the DevelopmentBoard connected with local GND potential
JP42 closed Input at opto-coupler U4 on the Development Boardconnected to P3.5 of the phyCORE-DS80C390
JP43 closed Output at opto-coupler U5 on the Development Boardconnected to P3.4 of the phyCORE-DS80C390
Table 33: Improper Jumper Settings for the CAN Plug P2A (CAN Transceiveron Development Board with Galvanic Separation)
1
2
3
4
7
6
5
8
9
phyCORE-DS80C390
66 PHYTEC Meßtechnik GmbH 2002 L-594e_1
14.3.6 RS-485 Interface or Second CAN Interface at Plug P2B
Connector P2B is the upper connector of the double DB-9 connectorat P2. Either the RS-485 interface or the second CAN interfacesignals of the phyCORE-DS80C390 can be routed to P2B viajumpers.
Depending on the configuration of the CAN transceivers and theirpower supply, the following three configurations are possible:
1. CAN transceiver U12 populating the phyCORE-DS80C390 isenabled and the CAN signals from the module extend directly toplug P2B.
Jumper Setting DescriptionJP33 2 + 4 Pin 2 of P2B is connected to CAN-L1 / C1Tx
from on-board transceiver on the phyCORE moduleJP34 2 + 3 Pin 7 of P2B is connected to CAN-H1 / C1Rx
from on-board transceiver on the phyCORE moduleJP14 open CAN opto-coupler U6 on the Development Board
disconnected from module pinsJP15 open CAN opto-coupler U7 on the Development Board
disconnected from module pinsJP13 open CAN transceiver and opto-coupler on the Development
Board disconnected from supply voltageJP18 open No GND potential at CAN transceiver and opto-coupler
on the phyCORE Development Board LD 5VJP29 open No power supply via CAN bus
Table 34: Jumper Configuration for CAN Plug P2B using the CAN Transceiveron the phyCORE-DS80C390
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 67
Pin 3: GND (Development Board Ground)Pin 7: CAN-H0 (not galvanically separated)Pin 2: CAN-L0 (not galvanically separated)Pin 6: GND (Development Board Ground)
Figure 25: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver onphyCORE-DS80C390)
Caution:When using the DB-9 plug P2B as CAN interface and the CANtransceiver on the phyCORE-DS80C390 the following jumpersettings are not functional and could damage the module:
Jumper Setting Description1 + 2 Pin 2 of DB-9 plug P2B connected with RS-485 A
signal from phyCORE-DS80C390JP33
2 + 3 Pin 2 of DB-9 plug P2B connected with CAN-L1 fromCAN transceiver U3 on the Development Board
JP34 1 + 2 Pin 7 of DB-9 plug P2B connected with CAN-H1signal from U3 on the Development Board
1 + 2 CAN opto-coupler U6 connected with CAN-L0 / C0Txof the phyCORE-DS80C390
JP14
2 + 3 CAN opto-coupler U6 connected with CAN-L1on the phyCORE-DS80C390
1 + 2 CAN opto-coupler U7 connected with CAN-H0 / C0Rxon the phyCORE-DS80C390
JP15
2 + 3 CAN opto-coupler U7 connected with CAN-H1 / C1Rxon the phyCORE-DS80C390
1 + 2 Supply voltage for CAN circuitry on the Dev. Boardderived from external source via on-board V regulator
JP13
2 + 3 Supply voltage for CAN circuitry derived from localsupply circuitry on the Development Board
JP18 closed CAN transceiver and opto-coupler on the DevelopmentBoard connected with local GND potential
JP29 closed Supply voltage for on-board voltage regulator frompin 9 of DB-9 connector P2A or P2B
Table 35: Improper Jumper Settings for the CAN Plug P2B (CAN Transceiveron phyCORE-DS80C390)
1
2
3
4
7
6
5
8
9
phyCORE-DS80C390
68 PHYTEC Meßtechnik GmbH 2002 L-594e_1
2. The CAN transceiver U12 populating the phyCORE-DS80C390 isdisabled; CAN signals generated by the CAN transceiver (U3) onthe Development Board extending to connector P2B withoutgalvanic seperation.
Note:The phyCORE-DS80C390 must be configured for external CANtransceiver to support this function (refer section 3.9)!
Jumper Setting DescriptionJP33 2 + 3 Pin 2 of DB-9 plug P2B connected with CAN-L1 from
CAN transceiver U3 on the Development BoardJP34 1 + 2 Pin 7 of DB-9 plug P2B connected with CAN-H1
signal from U3 on the Development BoardJP14 2 + 3 CAN opto-coupler U6 connected with CAN-L1/C1Tx
on the phyCORE-DS80C390JP15 2 + 3 CAN opto-coupler U7 connected with CAN-H1 / C1Rx
on the phyCORE-DS80C390JP13 2 + 3 Supply voltage for CAN circuitry derived from local
supply circuitry on the Development BoardJP18 closed CAN transceiver and opto-coupler on the Development
Board connected with local GND potentialJP29 open No power supply via CAN bus
Table 36: Jumper Configuration for CAN Plug P2B using the CAN Transceiveron the phyCORE-DS80C390
Pin 3: GND (Development Board Ground)Pin 7: CAN-H0 (not galvanically separated)Pin 2: CAN-L0 (not galvanically separated)Pin 6: GND (Development Board Ground)
Figure 26: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver onDevelopment Board)
1
2
3
4
7
6
5
8
9
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 69
Caution:When using the DB-9 connector P2B as CAN interface and the CANtransceiver on the Development Board the following jumper settingsare not functional and could damage the module:
Jumper Setting Description1 + 2 Pin 2 of DB-9 plug P2B connected with RS-485 A
signal from phyCORE-DS80C390JP33
2 + 4 Pin 2 of DB-9 plug P2B connected withCAN-L1/ C1Tx from phyCORE-DS80C390
JP34 1 + 2 Pin 7 of DB-9 plug P2B connected withCAN-H1/C1Rx from phyCORE-DS80C390
JP14 1 + 2 CAN opto-coupler U6 connected with CAN-L0 / C0Txof the phyCORE-DS80C390
JP15 1 + 2 CAN opto-coupler U7 connected with CAN-H0 / C0Rxon the phyCORE-DS80C390
JP13 1 + 2 Supply voltage for CAN circuitry on the DevelopmentBoard derived from external source via on-board
voltage regulatorJP18 open No GND potential at CAN transceiver and opto-coupler
on the phyCORE Development Board LD 5VJP29 closed Supply voltage for on-board voltage regulator from
pin 9 of DB-9 connector P2A or P2B
Table 37: Improper Jumper Settings for the CAN Plug P2B (CAN Transceiveron the Development Board)
phyCORE-DS80C390
70 PHYTEC Meßtechnik GmbH 2002 L-594e_1
3. The CAN transceiver U12 populating the phyCORE-DS80C390 isdisabled; CAN signals generated by the CAN transceiver (U3) onthe Development Board extend to connector P2A with galvanicseparation. This configuration requires connection of an externalCAN supply voltage of 7 to 13 V, 14 to 20 V or 21 to 27 V. Theexternal power supply must be only connected to either P2A orP2B.
Note:The phyCORE-DS80C390 must be configured for external CANtransceiver to support this function (refer section 3.9)!
Jumper Setting DescriptionJP33 2 + 3 Pin 2 of DB-9 plug P2B connected with CAN-L1 from
CAN transceiver U3 on the Development BoardJP34 1 + 2 Pin 7 of DB-9 plug P2B connected with CAN-H1
signal from U3 on the Development BoardJP14 2 + 3 CAN opto-coupler U6 connected with CAN-L1/C1Tx
on the phyCORE-DS80C390JP15 2 + 3 CAN opto-coupler U7 connected with CAN-H1 / C1Rx
on the phyCORE-DS80C390JP13 1 + 2 Supply voltage for CAN circuitry on the Development
Board derived from external source via on-boardvoltage regulator
JP18 open CAN transceiver and opto-coupler on the DevelopmentBoard disconnected from local GND potential
JP29 closed Supply voltage for on-board voltage regulatorfrom pin 9 of DB-9 plug P2B
1 + 2 external CAN supply of 7 to 13 V2 + 3 external CAN supply of 14 to 20 V
JP39
open external CAN supply of 21 to 27 V
Table 38: Jumper Configuration for CAN Plug P2B using the CAN Transceiveron the Development Board with Galvanic Separation
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 71
Pin 9: VCAN+
Pin 3: VCAN-Pin 7: CAN-H0 (galvanically separated)Pin 2: CAN-L0 (galvanically separated)Pin 6: VCAN-
Figure 27: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver onDevelopment Board with Galvanic Separation)
Caution:When using the DB-9 connector P2B as CAN interface and the CANtransceiver on the Development Board the following jumper settingsare not functional and could damage the module:
Jumper Setting Description1 + 2 Pin 2 of DB-9 plug P2B connected with RS-485 A
signal from phyCORE-DS80C390JP33
2 + 4 Pin 2 of DB-9 plug P2B connected withCAN-L1/ C1Tx from phyCORE-DS80C390
JP34 1 + 2 Pin 7 of DB-9 plug P2B connected withCAN-H1/C1Rx from phyCORE-DS80C390
JP14 1 + 2 CAN opto-coupler U6 connected with CAN-L0 / C0Txof the phyCORE-DS80C390
JP15 1 + 2 CAN opto-coupler U7 connected with CAN-H0 / C0Rxon the phyCORE-DS80C390
JP13 2 + 3 Supply voltage for CAN transceiver and opto-couplerderived from local supply circuitry on the
phyCORE Development Board LD 5VJP18 closed CAN transceiver and opto-coupler on the Development
Board connected with local GND potential
Table 39: Improper Jumper Settings for the CAN Plug P2B (CAN Transceiveron Development Board with Galvanic Separation)
1
2
3
4
7
6
5
8
9
phyCORE-DS80C390
72 PHYTEC Meßtechnik GmbH 2002 L-594e_1
The RS-485 interface is an alternative function of the serial interfacesignals on the DS80C390 controller. The default configuration of thephyCORE-DS80C390 activates the RS-232 interface. In order toenable the RS-485 signals, different jumper settings on thephyCORE-DS80C390 are required (refer to section 3.5 for details).
Jumper Setting DescriptionJP33 1 + 2 Pin 2 of DB-9 plug P2B connected with
RS-485 A signal on the phyCORE-DS80C390JP34 open Pin 7 of DB-9 plug P2B disconnected from
signals on the Development BoardJP14 open CAN opto-coupler U6 on the Development Board
disconnected from module pinsJP15 open CAN opto-coupler U7 on the Development Board
disconnected from module pinsJP13 open CAN transceiver and opto-coupler on the Development
Board disconnected from supply voltageJP18 closed Pin 3 and 6 of DB-9 plug P2B connected with local
GND potential on the Development BoardJP29 open Supply voltage via pin 9 of DB-9 connector
P2A or P2B disabledJP30 closed Pin 8 of DB-9 plug P2B connected with
RS-485 B signal on the phyCORE-DS80C390
Table 40: Jumper Configuration for DB-9 Plug P2B as RS-485 Interface
Pin 8: A Signal RS-485Pin 3: GND (Development Board Ground)
Pin 2: B Signal RS-485Pin 6: GND (Development Board Ground)
Figure 28: Pin Assignment of the DB-9 Plug P2B as RS-485 Interface
1
2
3
4
7
6
5
8
9
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 73
Caution:When using the DB-9 plug P2B as RS-485 interface, the followingjumper settings are not functional and could damage the module:
Jumper Setting Description2 + 3 Pin 2 of DB-9 plug P2B connected with CAN-L1 signal
from U3 on the Development BoardJP33
2 + 4 Pin 2 of DB-9 plug P2B connected with CAN-L1/C1Txon the phyCORE-DS80C390
1 + 2 Pin 7 of DB-9 plug P2B connected with CAN-H1signal from U3 on the Development Board
JP34
2 + 3 Pin 7 of DB-9 plug P2B connected with CAN-H1/C0Rx
on the phyCORE-DS80C3901 + 2 CAN opto-couler U6 connected with CAN-L0/C0Tx
of the phyCORE-DS80C390JP14
2 + 3 CAN opto-coupler U6 connected with CAN-L1/C1Txon the phyCORE-DS80C390
1 + 2 CAN opto-coupler U7 connected with CAN-H0/C0Rxon the phyCORE-DS80C390
JP15
2 + 3 CAN opto-coupler U7 connected with CAN-H1/C1Rxon the phyCORE-DS80C390
JP13 1 + 2 Supply voltage for CAN transceiver and opto-coupleron the Development Board derived from externalsource (CAN bus) via on-board voltage regulator
2 + 3 Supply voltage for CAN transceiver and opto-couplerderived from local supply circuitry on the
phyCORE Development Board LD 5VJP18 open Pin 3 and 6 of DB-9 connector P2B disconnected from
local GND potential on the Development BoardJP29 closed Supply voltage for on-board voltage regulator from
pin 9 of DB-9 connector P2A or P2B
Table 41: Improper Jumper Settings for the RS-485 Interface at Plug P2B
phyCORE-DS80C390
74 PHYTEC Meßtechnik GmbH 2002 L-594e_1
14.3.7 Programmable LED D3
The phyCORE Development Board LD 5V offers a programmableLED at D3 for user implementations. This LED can be connected to aport pin at GPIO0 (JP17 = 1+2) or the data bus via a latch atU14 (JP17 = 2+3). When using the phyCORE-DS80C390, the factorydefault configuration enables control of LED D3 using portpin P3.4 (GPIO0).
Control and illumination of the LED can also be enabled via usercode toggling data bit D0 at address 1400A0h. A low-level at latchU14 causes the LED to illuminate, LED D3 remains off when writinga high-level to latch U14.
Jumper Setting Description1 + 2 Port pin P3.4 (GPIO0) of the DS80C390 controller
controls LED D3 on the Development BoardJP17
2 + 3 Data bit D0 from the DS80C390 controller controlsLED D3 via latch U14 on the Development Board
Table 42: JP17 Configuration of the Programmable LED D3
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 75
14.3.8 Pin Assignment Summary of the phyCORE, theExpansion Bus and the Patch Field.
As described in section 14.1, all signals from thephyCORE-DS80C390 extend in a strict 1:1 assignment to theExpansion Bus connector X2 on the Development Board. Thesesignals, in turn, are routed in a similar manner to the patch field on anoptional expansion board that mounts to the Development Board atX2.
Please note that, depending on the design and size of the expansionboard, only a portion of the entire patch field is utilized under certaincircumstances. When this is the case, certain signals described in thefollowing section will not be available on the expansion board.However, the pin assignment scheme remains consistent.
A two dimensional numbering matrix similar to the one used for thepin layout of the phyCORE-connector is provided to identify signalson the Expansion Bus connector (X2 on the Development Board) aswell as the patch field.
phyCORE-DS80C390
76 PHYTEC Meßtechnik GmbH 2002 L-594e_1
However, the numbering scheme for Expansion Bus connector andpatch field matrices differs from that of the phyCORE-connector, asshown in the following two figures:
B A
D C
80
1
80
1
Figure 29: Pin Assignment Scheme of the Expansion Bus
A B C D E F
54
1
Figure 30: Pin Assignment Scheme of the Patch Field
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 77
The pin assignment on the phyCORE-DS80C390, in conjunction withthe Expansion Bus (X2) on the Development Board and the patchfield on an expansion board, is as follows:
Signal phyCORE-DS80C390 Expansion Bus Patch FieldP0.0/ D0 12C 18B 33FP0.1/ D1 13A 19A 34AP0.2/ D2 13C 20A 34EP0.3/ D3 14A 20B 34BP0.4/ D4 14B 21A 34DP0.5/ D5 14C 21B 34FP0.6/ D6 15A 22B 35AP0.7/ D7 15C 23A 35E
A0 6A 8B 30BA1 6B 9A 30DA2 6C 10A 30FA3 7A 10B 31AA4 7C 11A 31EA5 8A 11B 31BA6 8C 12B 31FA7 9A 13A 32A
P2.0 / A8 9B 13B 32CP2.1 / A9 9C 14A 32EP2.2 / A10 10A 15A 32BP2.3 / A11 10C 15B 32FP2.4 / A12 11A 16A 33AP2.5 / A13 11B 16B 33CP2.6 / A14 11C 17B 33EP2.7 / A15 12A 18A 33B
A16 16A 23B 35BA17 16B 24A 35DA18 16C 25A 35FA19 16D 24C 8B
Table 43: Pin Assignment Data/Address Bus for the phyCORE-DS80C390 /Development Board / Expansion Board
phyCORE-DS80C390
78 PHYTEC Meßtechnik GmbH 2002 L-594e_1
Signal phyCORE-DS80C390 Expansion Bus Patch FieldClkIn 1A 1A 28A
P3.2 / INT0 1C 2B 28EP3.3/ /INT1 2A 3A 28B
/CS1 3C 5A 29E/CS2 4A 5B 29B/CS3 4C 6B 29FALE 4B 6A 29D/RD 5A 7B 30A/WR 5C 8A 30E
/PCE2 (P5.6) 16E 25C 8D/PCE3 (P5.7) 16F 25D 8F
CLKRTC 10F 16C 5F
Table 44: Pin Assignment Control Signals for the phyCORE-DS80C390 /Development Board / Expansion Board
Signal phyCORE-DS80C390 Expansion Bus Patch FieldBOOT 6D 9C 3B
/RESET 6E 10C 3D/RESIN 6F 10D 3F
/RESOUT 7F 11C 4ET0 (P3.4) 7D 11D 4AT1 (P3.5) 8D 12D 4B
RxD (P3.0) 11D 16D 6ATxD (P3.1) 11E 17D 6C
RSTxD 14F 22D 7FRSRxD 15F 23D 8E
CAN-H1 / C1Rx 13D 20C 7ACAN-L1 / C1Tx 12D 18D 6BCAN-L0 / C0Tx 14D 21C 7BCAN-H0 / C0Rx 15D 23C 8A
A 14E 21D 7DB 13F 20D 7E
SCL 11F 18C 6ESDA 12F 19C 6FP4.2 8F 13C 4FP4.3 9D 13D 5A
Table 45: Pin Assignment Interface Signals for the phyCORE-DS80C390 /Development Board / Expansion Board
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 79
Signal phyCORE-DS80C390 Expansion Bus Patch FieldPFI 4F 7D 2FPFO 5F 8C 3EVCC 1D, 2D 1C, 2C, 1D, 2D 1A, 1CVPD 4E 6D 2D
VBAT 4D 6C 2BGND 2b, 3B, 5B, 7B, 8B,
10B, 12B, 13B, 15B,5E, 7E, 8E, 10E, 12E,
13E, 15E,1F, 2F, 3F
2A, 7A, 12A,17A, 22A, 27A,32A, 37A, 42A47A, 52A, 57A,62A, 67A, 72A,
77A,4B, 9B, 14B,
19B, 24B, 29B,34B, 39B, 44B,49B, 54B, 59B,64B, 69B, 74B,
79B,3C, 7C, 12C,
17C, 22C, 27C,32C, 37C, 42C47C, 52C, 57C,62C, 67C, 72C,
77C,3D, 9D, 14D,
19D, 24D, 29D,34D, 39D, 44D,49D, 54D, 59D,64D, 69D, 74D,
79D
3C, 4C, 7C, 8C,9C, 12C, 13C,14C, 17C, 18C,19C, 22C, 23C,24C, 27C, 29C,30C, 31C, 34C,35C, 36C, 39C,40C, 41C, 44C,45C, 46C, 49C,50C, 51C, 54C,
4D, 5D, 6D,9D,10D; 11D,
14D, 15D, 16D,19D, 20D, 21D,24D, 25D, 26D,28D, 31D, 32D33D, 36D, 37D,38D, 41D, 42D,43D, 46D, 47D,48D, 51D, 52D,
53D
Table 46: Pin Assignment Power Supply for the phyCORE-DS80C390 /Development Board / Expansion Board
phyCORE-DS80C390
80 PHYTEC Meßtechnik GmbH 2002 L-594e_1
Signal phyCORE-DS80C390 Expansion Bus Patch FieldNC 3A, 1B, 2C, 2D,
3D, 10D, 2E,3E, 9E, 9F,
10F,
3A, 4A, 1B, 4C,5C, 14C, 15C,16C, 4D, 5D,
15D
2A, 29A, 1B, 5B,2C, 5C, 28C,1D, 5E, 5F,
28FPins on theDevelopmentBoard not beingused by thephyCORE-DS80C390
17A to 32A17B to 32B17C to 32C17D to 32C17E to 32E17F to 32F
except GND pins inrow B and E
see GPIOHardwareManual
see GPIOHardware Manual
Table 47: Unused Pins on the phyCORE-DS80C390 / Development Board /Expansion Board
14.3.9 Battery Connector BAT1
The mounting space BAT1 (see PCB stencil) is provided forconnection of a battery that buffers volatile memory devices (SRAM)and the RTC on the phyCORE-DS80C390. The Voltage SupervisorChip on the phyCORE-DS80C390 is responsible for switching from anormal power supply to a back-up battery. This optional batteryrequired for this function (refer to section 11) is available throughPHYTEC (order code BL-003).
The phyCORE-DS80C390 on the phyCORE Development Board
PHYTEC Meßtechnik GmbH 2002 L-594e_1 81
14.3.10 DS2401 Silicon Serial Number
Communication to a DS2401 Silicon Serial Number can be imple-mented in various software applications for the definition of a nodeaddress or as copy protection in networked applications. The DS2401can be soldered on space U10 or U9 on the Development Board,depending on the type of device packaging being used.
The Silicon Serial Number Chip mounted on the phyCOREDevelopment Board LD 5V can be connected to a port pin atGPIO1 (JP19 = 1+2) or the data bus via latch U14 and driverU15 (JP19 = 2+3). When using the phyCORE-DS80C390, the factorydefault configuration enables access to the Silicon Serial Numberusing port pin P3.5 (GPIO1).
As an alternative, access to the DS2401 Silicon Serial Number can beenabled via user code by means of data bit D1 at address 1400A0h(JP19 = 2+3).
Jumper Setting Description1 + 2 Port pin P3.5 (GPIO1) of the DS80C390
is used to access the Silicon Serial NumberJP19
2 + 3 Data bit D1 of the DS80C390 is used to access theSilicon Serial Number via latch U14 / driver U15
Table 48: JP19 JumperConfiguration for Silicon Serial Number Chip
phyCORE-DS80C390
82 PHYTEC Meßtechnik GmbH 2002 L-594e_1
Figure 31: Connecting the DS2401 Silicon Serial Number
Figure 32: Pin Assignment of the DS2401 Silicon Serial Number
14.3.11 Pin Header Connector X4
The pin header X4 on the Development Board enables connection ofan optional modem power supply. Connector X4 supplies 5 V = atpin 1 and provides the phyCORE Development Board LD 5V GNDpotential at pin 2. The maximum current draw depends on the poweradapter used. We recommend the use of modems with less than250 mA current draw.
notconnected U14/U15NUMPORT
Port P3.5
JP19
Index
PHYTEC Meßtechnik GmbH 2002 L-594e_1 83
Index
/
/PCE2 ........................................19/PCE3 ........................................19
A
Address Decoder .......................25Address Decoder Control
Registers.................................30
B
BAT1.........................................81Battery Buffer............................42Battery Connector .....................81Block Diagram ............................6BOOT........................................30
C
CAN Bus ...................................34CAN Interface ...............34, 60, 67CAN Transceiver ......................34CANH .......................................34CANL........................................34Concept of the Development
Board ......................................47Connector X4 ............................83
D
Default Memory Model.............25Development Board
Connectors and Jumpers ........49DS2401......................................82
E
EMC ............................................1EMI ...........................................34Expansion Bus...........................76
F
FA20..........................................31Features .......................................5First Serial Interface ..................57Flash Memory............................35Functional Components on the
phyCOREDevelopment Board................53
H
Hints for Handling the Module .45HS_EN.......................................31
I
I²C Bus.......................................21Introduction .................................3
J
J1 ...............................................18J10 .............................................20J11 .............................................23J12 .............................................23J13 .............................................21J16 .............................................23J17 .............................................23J18 .............................................22J19 .............................................22J2 ...............................................18J2 ...............................................18J20 .............................................22J21 .............................................22J22 .............................................23J3 ...............................................19J4 ...............................................19J5 ...............................................19J6 ...............................................19
phyCORE-DS80C390
84 PHYTEC Meßtechnik GmbH 2002 L-594e_1
J7 ............................................... 19J8 ............................................... 20J9 ............................................... 20JP17........................................... 75JP19........................................... 82Jumper Configuration ............... 50Jumper Settings ......................... 17
L
LED D3..................................... 75
M
Memory Model ......................... 25MUX_ENA............................... 30
P
P4.2 ........................................... 21P4.3 ........................................... 21P5.6 ........................................... 19P5.7 ........................................... 19Patch Field ................................ 76phyCORE-connector............. 9, 12Physical Dimensions ................. 43Pin Assignment ......................... 76Pin Description............................ 9Pinout ........................................ 14Plug P2A ................................... 60Plug P2B ................................... 67Power Consumption.................. 44Power Supply ............................ 53
R
Real-Time Clock....................... 39Remote Supervisory Chip ......... 41Reset Button.............................. 50Reset Controller ........................ 40RS-232 Interface ....................... 33RS-232 Transceiver ............ 20, 33
RS-485 Interface .................33, 67RS-485 Transceiver.............20, 33RTC...........................................42RTC Clockout ...........................23RTC Interrupt Output................21
S
SCL ...........................................21SDA...........................................21Serial .........................................38Silicon Serial Number ...............82Socket P1A (First RS-232)........57Socket P1B................................58SRAM .................................18, 42Starting FlashTools ...................55
T
Technical Specifications ...........43
U
U10......................................20, 33U11......................................20, 33U12............................................34U13............................................34U3..............................................18U4..............................................18U5..............................................35U6..............................................39U7..............................................38U8..............................................40U9..............................................41
V
VBAT........................................42VCC...........................................18VN_ENA...................................31VPD...........................................18
Suggestions for Improvement
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PHYTEC Meßtechnik GmbH 2002 Ordering No. L-594e_1Printed in Germany