Technische Universität Berlin Seyed Saeed Fazel von der Fakultät IV- Elektrotechnik und Informatik der Technischen Universität Berlin Institut für Energie- und Automatisierungstechnik Zur Erlangung des akademischen Grades eines Doktoringenieurs (Dr.-Ing.) genehmigte Dissertation Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications Vorsitzender: Prof. Dr.-Ing. C. Boit Gutachter: Prof. Dr.-Ing. S. Bernet Prof. Dr.-Ing. U. Schäfer Prof. Dr.-Ing. M. Michel Tag der Einreichung: 11.07.2007 Tag der Verteidigung: 23.08.2007 Berlin 2007 D 83
Transcript
Technische Universität Berlin
Seyed Saeed Fazel
von der Fakultät IV- Elektrotechnik und Informatik der Technischen Universität Berlin
Institut für Energie- und Automatisierungstechnik
Zur Erlangung des akademischen Grades eines
Doktoringenieurs
(Dr.-Ing.)
genehmigte Dissertation
Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications
Vorsitzender: Prof. Dr.-Ing. C. Boit Gutachter: Prof. Dr.-Ing. S. Bernet
Prof. Dr.-Ing. U. Schäfer Prof. Dr.-Ing. M. Michel
Tag der Einreichung: 11.07.2007 Tag der Verteidigung: 23.08.2007
Berlin 2007 D 83
Seyed Saeed Fazel
Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications
Preface
I would like to express my sincere gratitude to my supervisor, Professor Dr.-Ing. Steffen Bernet for his professional guidance, interesting discussion and encouragement throughout the period of this research. I would also like to thank my friends and colleagues in the Power Electronics Group of Berlin University. In particular, I would like to acknowledge Dietmar Krug and Kamran Jalili. The author wishes to acknowledge the financial support of Iran Ministry of Science, Research and Technology scholarship. Finally, my personal thanks are extended to my family and friends for their support.
Seyed Saeed Fazel Berlin, July 2007
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TABLE OF CONTENTS
Glossary of Symbols and Acronyms ....................................................................... iv
List of Figures .......................................................................................................... x
List of Tables ............................................................................................................ xvii
2. Overview of Medium Voltage Converter Topologies ....................................... 2.1. State of the Art in Medium Voltage Converters ............................................. 2.2. State of the Art in Medium Voltage Power Semiconductors...........................
336
3. Basic Structure and Function of Multi-Level Voltage Source Converter Topologies …………………………………………...………………………..
3.1. Two-Level Voltage Source Converter (2L-VSC) ............................................. 3.1.1. Structure of Two-Level Voltage Source Converter (2L-VSC).................... 3.1.2. Switch States and Commutations ................................................................ 3.1.3. Sine-Triangle Modulation ............................................................................ 3.1.4. Output Waveforms and Spectrum ...............................................................
3.2. Diode Clamped Voltage Source Converter (DC VSC) .................................... 3.2.1. Structure ....................................................................................................... 3.2.1.1. Three-Level Neutral Point Clamped Voltage Source Converter (3L-
NPC VSC)................................................................................................ 3.2.1.1.1. Switch States and Commutations ....................................................... 3.2.1.1.2. Sine-Triangle Modulation ..................................................................
VSC)………………………………………………………………….. 3.3.1.1.1. Switch States and Commutations....................................................... 3.3.1.1.2. Sine-Triangle Modulation...................................................................
3.3.1.2. Four-Level Flying Capacitor Voltage Source Converter (4L-FLC VSC).........................................................................................................
3.4. Series Connected H-Bridge Voltage Source Converter (SCHB VSC) ……... 3.4.1. Single-Phase Full-Bridge (H-Bridge) Topology ........................................ 3.4.1.1. Circuit Configuration ............................................................................... 3.4.1.2. Switch States and Commutations ............................................................ 3.4.1.3. Sine-Triangle Modulation........................................................................
3.4.2. Three-Phase Two-Level H-Bridge (2L-H-Bridge) Topology ................... 3.4.2.1. Circuit Configuration ............................................................................... 3.4.2.2. Switch States and Commutations............................................................. 3.4.2.3. Sine-Triangle Modulation........................................................................
9999
11121414
1516192222
232325
28323232333638383939
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3.4.3. Introduction to the Series Connected Two-Level H-Bridge Voltage Source Converter (SC2LHB VSC)……………..........................................
3.4.3.1. Series Connected Two-Level H-Bridge Voltage Source Converter with Two Power Cells per Phase Leg (5L-SC2LHB VSC)....................
3.4.3.1.1. Circuit Configuration.......................................................................... 3.4.3.1.2. Switch States and Commutations........................................................ 3.4.3.1.3. Sine-Triangle Modulation...................................................................
3.4.3.2. Series Connected Two-Level H-Bridge Voltage Source Converter with Three Power Cells per Phase Leg (7L-SC2LHB VSC)..................
3.4.3.2.1. Circuit Configuration.......................................................................... 3.4.3.2.2. Switch States and Commutations....................................................... 3.4.3.2.3. Sine-Triangle Modulation...................................................................
3.4.3.3. Series Connected Two-Level H-Bridge Voltage Source Converter with Four Power Cells per Phase Leg (9L-SC2LHB VSC)....................
3.4.4. N-Level Series Connected Three-Level H-Bridge Voltage Source Converter (NL- SC3LHB VSC) ...............................................................
3.4.4.1. Circuit Configuration of Five-Level Series Connected 3-Level H-Bridge Voltage Source Converter (5L-SC3LHB VSC)..........................
3.4.4.2. Switch States and Commutations............................................................. 3.4.4.3. Sine-Triangle Modulation........................................................................
4.2.1.2.1. Power Semiconductor Losses…………………………………….. 4.2.1.2.2. Loss Approximation based on Datasheets………………………… 4.2.1.2.3. Description of the Loss Simulation Model……………………….. 4.2.1.2.4. Agreement Calculation Measurement……………………………...
4.2.2. DC Link Capacitor Models..……………………………………………. 4.2.2.1. Capacitor................................................................................................
4.2.2.1.1. Aluminium Electrolytic Capacitors ...……………………………. 4.2.2.1.2. Film Capacitors …………………………………………………...
4.3.1.3. Medium Voltage Converter Application............................................... 4.3.1.3.1. Three-Level Neutral Point Clamped Voltage Source Converter.....
4.3.1.3.1.1. Simulation Results................................................................. 4.3.1.3.2. Nine-Level Series Connected H-Bridge Voltage Source Converter
5. Design Criteria and Converter Data……........................................................... 5.1. Design Criteria………………………………………………………………
5.1.1. Power Semiconductor Devices…..……………………………………... 5.1.2. DC Link Capacitor………………………………………………………
5.1.2.1. DC Link Voltage Ripples..……………………………………………
5.1.2.2. DC Link Capacitor Stored Energy……………………………………
5.1.2.3. Design of the Flying Capacitors………………………………………
5.2. Definition of the Converter Data..................................................................... 5.2.1. Power Semiconductor Devices................................................................. 5.2.2. Switching Frequency................................................................................. 5.2.3. DC Link Voltage.......................................................................................... 5.2.4. Rectifier………………………………………………….......................... 5.2.5. General Data for the Selective Medium Voltage Converter......................
959595
100100100101102102103103103103
6. Converter Comparison........................................................................................ 6.1. Comparison of Power Semiconductor Utilization and Loss Distribution......... 6.1.1. Comparison at Constant Installed Switch Power and Constant Carrier
Frequency..................................................................................................... 6.1.2. Comparison of Maximum Carrier Frequency at Constant Installed
Switch Power and Constant Apparent Converter Output Power............................................................................................................
6.1.3. Comparison of Converter Power and Loss Distribution at for Constant Installed Switch Power and Constant Frequency of the First Carrier Band
6.1.4. Comparison of 4.16kV, 4.32MVA Multi-Level Converters at Constant Efficiency………………………………………………………………..
6.2. Comparison of Power Semiconductor Utilization and Power Loss Distribution for 2.3kV-6kV Multi-Level Converters (3L-NPC VSC and SC2LHB VSCs)..................................................................................................
6.3. Comparison of the DC Link Capacitor for a 24-pulse, 4.16kV, 4.32MVA, 3L-NPC VSC and 9L-SC2LHB VSC………………………………………
107107
107
112
118
123
127
130
7. Conclusion and Discussion …………………………………………………… 143
Variable Meaning a, b, c AC terminals of the converter Aon,x On state resistance for device x Asw,off,x, Bsw,off,x Turn-off curve-fitting constants for device x Asw,on,x, Bsw,on,x Turn-on curve-fitting constants for device x Bcon,x Curve-fitted constant for device x Cjx Flying capacitor (j = 1, .., N-1), (x = a, b, c) Cmin,NPC Minimum size of the dc link capacitance for NPC converter Cmin,SCHB Minimum size of the dc link capacitance for SCHB converter Cx DC link capacitance (x = 1, .., N-1) cosϕ Load power factor Djkx, jkxD H-bridge diodes (j = 1, 2, ... p), (k = L, R), (x = a, b, c) Djx NPC diodes (j = 1, .., N-1), (x = a, b, c)
i ijx jxD ,D Series connected three-level H-bridge NPC diodes (j = 1, 2), (x = a, b, c), (i = 1, 2)
i iTjkx TjkxD ,D 3L-H-Bridge freewheeling diodes (j = 1, 2, ... p), (k = 1, 2), (x = a, b, c), (i = 1, 2),
DTjx, TjxD freewheeling diodes (x = a, b, c), (j = 1, .., N-1) EC Stored energy in the dc link capacitor Eon, Eoff, Erec Turn-on, turn-off energy in IGBT and recovery energy in diode Esw,x Switching energy loss for device x ex Load electromotive force (x = a, b, c) f1 Fundamental output frequency fC Carrier frequency fC,max Maximum carrier frequency fC1b Frequency of the first harmonics carrier band fh Frequency of harmonics order fo Converter output frequency frec Rectifier output frequency ftri Frequency of triangle carrier signal g H-bridge negative dc rail gs Gate signal h Ordinal number of harmonic i(t) Instantaneous value of current
I´sx Transformer secondary windings current referred to the primary side (x = 1,.., 4)
IC Collector current IC,n Collector current in IGBT IF,n Forward current in diode Ih Amplitude of the harmonic current Iph,max Maximum value of the output phase current Iph,rms,1 Effective value of the output phase current
1ph,rms ,I Peak value of the output phase current Ipx Transformer primary winding current (x = 1, 2) Isx Transformer secondary winding current (x = 1, 2, 3, 4) iC Rating capacitor current
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iC,j DC link capacitor current (j = 0, .., N-1) iC,rip Effective ripple current in the capacitor iC,rms Effective current of flying capacitor cells iCj,x Flying capacitor current (j = 1, 2, ..), (x = a, b, c), idc,j Current at any node of the capacitor bank (j = 0, .., N-1) idcjx Capacitor current at each H-bridge (j = 1, 2, ... p), (x = a, b, c) iLx Load current (x = a, b, c) io Transformer no-load primary current
phi Peak value of the phase current iph Output phase current iph,a a-phase current isx Utility grid phase current (x = A, B, C) k11, k21, k22 Transformer turn ratio between secondary windings L1 Transformer primary inductance LESR Equivalent series inductance LL Load inductance Lm Transformer magnetization inductance LmY, LmD Transformer equivalent inductance with star and delta connections Ls Utility grid inductance Lx1jY, Lx1jD Transformer primary leakage inductance (x = U, V, W), (j = 1, 2) Lx2jY, Lx2jD Transformer secondary leakage inductance (x = U, V, W), (j = 1, 2, 3, 4) M, Mj Converter midpoint (j = 0, .., N-1) N Number of level voltage per phase leg ma Amplitude modulation ratio mf Frequency modulation ratio n Load star point n´ Converter star point n11 Number of primary turn winding n2jx Number of secondary turn windings (j = 1, 2), (x = Y, D) nc Number of series capacitors nC Number of series connected flying capacitor cells
nj1YD Transformer secondary windings turn ratio between delta and star connections (j = 1, 2)
nsw Number of switch states nT, nD Number of semiconductors and diodes in the converter ntr Transformer open circuit turns ratio PC Converter output active power Pcon,x Conduction losses in device x PconD Conduction losses of diodes PconT Conduction losses of IGBT Ploss Power dissipation loss Ploss,D Power dissipation loss in a freewheeling diode Ploss,T Power dissipation loss in an IGBT PoffD Turn-off losses of diode PoffT Turn-off losses of IGBT PonT Turn-on losses of IGBT Psw,x Average switching loss in device x p Number of single-phase H-bridge cell per phase leg ph Number of phase R1 Transformer primary resistance
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R1jD Transformer primary winding resistance (j = 1, 2) R2jx Transformer secondary winding resistance (j = 1, 2), (x = Y, D) REPR Bypass resistance RESR Equivalent series resistance RL Load resistance Rm Transformer magnetization resistance Rs Utility grid resistance RT Transformer resistance Rth Thermal resistances Rth,ch Thermal resistances from junction to case Rth,ch,T, Rth,ch,D Thermal resistances of the IGBT and diode from junction to case Rth,ha Thermal resistances from heat sink to ambient Rth,jc Thermal resistances from case to heat sink Rth,jc,T, Rth,jc,D Thermal resistances case to heat sink of IGBT and diode SC Converter three-phase apparent power SC,max Maximum apparent converter output power SCR Relative apparent converter output power Sin Inner switches Sjkx, jkxS Two-level H-bridge switches (i = 1,...p), (k = L, R), (x = a, b, c)
i ijkx jkxS ,S Three-level H-bridge switches (j = 1,...p), (k = 1, 2), (x = a, b, c), (i = 1, 2)
Sjx, jxS Switches (j = 1, .., N-1), (x = a, b, c)
Skx, kxS Series connected H-bridge switches (k = L, R), (x = a, b, c) SN1 Transformer apparent rated power Sout Outer switches SS Installed switch power SSR Relative installed switch power T1 Fundamental period Ta Ambient temperature tanδ Dissipation factor of capacitor TC Period of carrier frequency Th Heat sink temperature Tj, Tj(x) Junction temperature (x = T, D) Tj,max Maximum junction temperature Tj,sp Specified junction temperature Tjkx, jkxT Two-level H-bridge transistor (j = 1,...p), (k = L, R), (x = a, b, c)
i ijkx jkxT ,T Three-level H-bridge transistors (j = 1,...p), (k = 1, 2), (x = a, b, c), (i = 1, 2)
Tjx, jxT Transistors (j = 1, .., N-1), (x = a, b, c)
Tkx, kxT , Tk, kT H-bridge transistor (k = L, R), (x = a, b, c) t Time Uab, Ubc, Uca Specific line-to-line voltages Uax, Un´x Specific output leg voltages (x = g, M1) UC Capacitor operating voltage UCE Collector-emitter voltage UCE,n On-state saturation voltage in IGBT UCjx Flying capacitor voltage (j = 1, 2), (x = a, b, c) Ucom Commutation voltage
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Ucom@100FIT Commutation voltage for a device reliability of 100FIT Ucon, Ucon,x Reference voltage per phase (x = a, b, c) Ûcon,1 Peak value of the desired fundamental component of the reference voltage UCx DC link capacitor voltage (x = 1, 2, ...) Udc DC link voltage for 2L-VSC, 3L-VSCs, and 4L-FLC VSC Udc,3L-HB DC link voltage of one H-bridge in SC3LHB VSC Udc,HB DC link voltage of one H-bridge in SC2LHB VSC Udc,min Minimum dc link voltage Udc,n Nominal dc link voltage Udc,tv Total virtual dc link voltage for SC2LHBVSCs, and SC3LHBVSCs Udcjx H-bridge dc link voltage (j = 1, .., p), (x = a, b, c) UF,n On-state voltage in diode Ujxn´ H-bridge output voltage (j = 1, .., p), (x = a, b, c) Ujxn´ Specific line-to-ground x-phase voltage for H-bridge (j = 1, .., p) Uk Transformer short-circuit voltage
Uk12Y, Uk12D Transformer short-circuit voltage between primary and secondary windings
Uk2YD Transformer short-circuit voltage between secondary star and delta windings
Ull,rms,1 Effective value of line-to-line output voltage UnM Specific common-mode voltage Uo,x Threshold voltage in device x URRM Rated repetitive peak reverse voltage of diodes Usx Utility grid phase voltage (x = A, B, C) Ûtri Peak value of triangular wave Utri,cell,j, Utri,kj Amplitude of triangle carrier signal (j = 1, 2, …), (k = L, R) Utri,Utri,j,Utri,j,x Utri,i Amplitude of triangle carrier signal (j = up, low), (x = a, b), (i = 1, 2) Ux x-phase line-to-ground voltage (x = a, b, c) UxM Specific phase-midpoint output voltage (x = a, b, c) Uxn Specific line-to-neutral voltages (x = a, b, c) Uxn´ Specific H-bridge output voltage (x = a, b, c)
Tj T j Tj,x Tj,x
Tk,x Tk,x T1j,xi T1j,xi
g g g g
g g g g
V ,V ,V ,V ,V ,V ,V ,V
Gate signals (j = 1, 2, …), (x = a, b, c), (k = L, R), (i = 1, 2)
X1j Transformer primary voltage (X = U, V, W), (j = 1, 2) X2jk Transformer secondary voltage (X = U, V, W), (j = 1, 2, 3, 4), (k = Y, D) XN1 Transformer primary rated voltage (X = U, V, W)
XN10Y, XN10D Transformer primary no-load voltages with star and delta connections (X = U, V, W)
XN20Y, XN20D Transformer secondary no-load voltages with star and delta connections (X = U, V, W)
ZN11Y Transformer primary winding rated impedance ZT Transformer impedance α Transformer phase displacement between primary and secondary αp Transformer phase displacement ∆UC DC link capacitor voltage ripples ∆UC,max Maximum dc link capacitor voltage ripples φ Load current angle ω1 Fundamental angular frequency η Efficiency
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Acronyms and Abbreviations Acronym/Name Meaning ANSI American National Standard BJT Bipolar Junction Transistor CD Carrier Disposition Modulation CSC Current Source Converter CSI Current Source Inverter D Diode DC VSC Diode Clamped Voltage Source Converter Dd Delta-delta Configuration Dy Delta-star Configuration Dzz Delta-zigzag-zigzag Configuration EMF Electromotive force EMI Electromagnetic Interference FIT One failure in 109 operation hours FLC Flying Capacitor GCT Gate-commutated Thyristor GTO Gate Turn-Off Thyristor H Hybrid Modulation HV-IGBT High Voltage Insulated Gate Bipolar Transistor IEEE Institute of Electrical and Electronics Engineers IGBT Insulated Gate Bipolar Transistor IGCT Integrated Gate Commutated Thyristor LV-IGBT Low Voltage Insulated Gate Bipolar Transistor MCT MOS-controlled Thyristor ML Multi-Level MLC Multi-Level Converter MOSFET Metal Oxide Semiconductor Field Effect Transistor MPC Multiple Point Clamped MTO MOS Turn-Off Thyristor MV Medium Voltage MVD Medium Voltage Drive N Number of Voltage Level NEMA National Electrical Manufacturers Association NPC Neutral Point Clamped OP Operating Point PD Phase Disposition POD Phase Opposition Disposition PS Phase Shifted Modulation PWM Pulse-Width-Modulated SC2LHB Series Connected Two-Level H-Bridge SC3LHB Series Connected Three-Level H-Bridge SCHB Series Connected H-Bridge SVM Space Vector Modulation T Transistor THD Total Harmonic Distortion VSC Voltage Source Converter VSI Voltage Source Inverter WTHD Weighted Total Harmonic Distortion Zdy Zigzag-delta-star Configuration
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List of Figures Figure 2-1: Application ranges of commercially available power semiconductors Figure 2-2: IGBT-based inverter fed medium voltage drives: (a) 3L-NPC, (b) SCHB Figure 2-3: Classification of state-of-the-art power semiconductors Figure 2-4: Power range of commercially available power semiconductors Figure 2-5: Application ranges of IGBTs and IGCTs
Figure 3-1: Two-Level Voltage Source Configuration
Figure 3-2: Switch states: (a) conduction paths, (b) commutations and switching losses for each phase of the 2L-VSC
Figure 3-3: Voltage waveforms of the 2L-VSC: (a) control signals Ucon, x and triangular signal Utri, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage
Figure 3-4: Harmonic spectrum of the 2L-VSC: (a) phase-midpoint output voltage, (b) line-to-line output voltage
Figure 3-5: One-phase N-Level Neutral Point Clamped Converter
Figure 3-6: Three-phase Three-Level Neutral Point Clamped Converter
Figure 3-7: Conduction path of the Three-Level Neutral Point Clamped Converter
Figure 3-8: Commutations and switching losses in the 3L-NPC VSC: (a) and (b) for positive load current, (c) and (d) for negative load current
Figure 3-9: Voltage waveforms of the 3L-NPC VSC: (a) control signals Ucon, x and triangular signals Utri,up and Utri,low, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage
Figure 3-10: Harmonic spectrum of the 3L-NPC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
Figure 3-11: The generalized N-Level Flying Capacitor Converter
Figure 3-13: Conduction path of the Three-Level Flying Capacitor Converter
Figure 3-14: Commutations and switching losses in the 3L-FLC Converter (a-d) for positive load current, (e-h) for negative load current
Figure 3-15: Voltage waveforms of the 3L-FLC VSC: (a) control signals and triangular signals, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage
Figure 3-16: Harmonic spectrum of the 3L-FLC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
Figure 3-18: Voltage waveforms of the 4L-FLC VSC: (a) control signals and triangular signals, (b) phase-midpoint output voltage, (c) line-to-line output voltage, (d) common mode voltage
Figure 3-19: Harmonic spectrum of the 4L-FLC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
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Figure 3-20: Transitions between voltage levels for the Four-Level Flying Capacitor
Figure 3-21: Three-phase configuration for the N-Level H-Bridges VSC
Figure 3-22: Typical power cell (H-bridge) converter
Figure 3-23: Conduction path of the single-phase H-bridge cell: (a) positive, (b, c) zero, and (d) negative states
Figure 3-24: Commutations and switching losses in the H-bridge cell: (a) and (b) for positive load current, (c) and (d) for negative load current
Figure 3-25: Voltage waveforms of the H-bridge cell: (a) control signals Ucon and triangular signals Utri,1 and Utri,2, (b) output voltage of leg a, (c) output voltage of leg n´, (d) load voltage
Figure 3-26: Harmonic spectrum of the H-bridge output voltage
Figure 3-27: Three-phase configuration for the 2L-H-Bridges Voltage Source Converter
Figure 3-28: Voltage waveforms of the three-phase 2L-H-Bridge cell: (a) control signals Ucon,x and triangular signals Utri,1 and Utri,2, (b) gate signals, (c) output phase voltage, (d) output line-to-line voltage
Figure 3-29: Harmonic spectrum of the three-phase 2L-H-Bridge cell: (a) phase output voltage, (b) line-to-line output voltage
Figure 3-30: Series Connected Two-Level H-Bridge Voltage Source Converter with p series H-bridge cells per phase
Figure 3-31: 5L-SC2LHB Voltage Source Converter
Figure 3-32: Transitions between voltage levels for the 5L-SC2LHB VS
Figure 3-33: Conduction path of the 5L-SC2LHB VSC
Figure 3-34: Voltage waveforms of the 5L-SC2LHB VSC: (a) control signals Ucon,x and triangular signals Utri,L1, Utri,L2, Utri,R1 and Utri,R2, (b) gate signals, (c) output phase-to-ground voltage Uan´, (d) output line-to-line voltage Uab, (e) output load-phase voltage Uan
Figure 3-35: Harmonic spectrum of the 5L-SC2LHB VSC
Figure 3-36: Pulse width modulation for the 7L-SC2LHB VSC: (a) control signals Ucon,a and triangular signals Utri,Li and Utri,Ri, (b) gate signals (mf = 3)
Figure 3-37: Voltage waveforms of the 7L-SC2LHB VSC: (a) reference and triangular signals, (b) output phase voltage Uan, (c) output line-to-line voltage Uab, (d) output load-phase voltage Uan´ (mf = 15)
Figure 3-38: Harmonic spectrum of the phase voltage (a) and line-to-line voltage (b) of the 7L-SC2LHB VSC
Figure 3-39: The 9L-SC2LHB Voltage Source Converter
Figure 3-40: Pulse width modulation for the 9L-SC2LHB VSC: (a) control signals Ucon,a and triangular signals Utri,Li and Utri,Ri, (b) gate signals (mf = 3)
Figure 3-41: Voltage waveforms of the 9L-SC2LHB VSC: (a) reference and triangular signals, (b) output phase voltage Uan´, (c) output line-to-line voltage Uab, (d) output load-phase voltage Uan (mf = 15)
Figure 3-42: Harmonic spectrum of the phase voltage Uan´ (a) and the line-to-line voltage Uab
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(b) of the 9L-SC2LHB VSC
Figure 3-43: NL-SC3LHB VSC with p series 3L-H-Bridge cells per phase
Figure 3-45: Voltage waveforms of the 5L-SC3LHB VSC: (a) control signal Ucon and triangular signals, (b) a1-leg gate signals, (c) a1-leg phase voltage, (d) a2-leg gate signals, (e) a2-leg phase voltage, (f) converter output voltage
Figure 3-46: Harmonic spectrum of the 5L-SC3LHB VSC
Figure 3-47: Number of total components required in the multi-level converter as a function of the number of phase voltage levels
Figure 4-1: Block diagram of Medium Voltage Drives: (a) NPC and FLC VSCs, (b) SCHB VSC
Figure 4-2: Standard load model for one-phase and three-phase
Figure 4-3: Standard three-phase utility grid model
Figure 4-4: The ideal circuit symbol of the IGBT
Figure 4-5: The steady state equivalent thermal circuit diagram: (a) general model, (b) Infineon model
Figure 4-6: Characteristics of current sharing for two connected modules in parallel
Figure 4-7: Approximation characteristics based on the curve-fitting method: (a) IGBT/Diode on-state characteristics, (b) IGBT turn-on and IGBT/Diode turn-off switching energy (FZ800R33KF2C IGBT-module from Eupec, UCE = 1800V, Tj,max = 125°C)
Figure 4-8: Equivalent circuit of a capacitor
Figure 4-9: Circuit diagram of the standard six-pulse diode rectifier
Figure 4-12: Investigated zigzag coupling configurations: (a) Delta-zigzag-zigzag configuration (Dzz), (b) Zigzag-delta-star configuration (Zdy) used by the industry
Figure 4-13: Windings position for positive (a), and negative (b) phase shift of Dzz configuration
Figure 4-14: Windings position for positive (a), and negative (b) phase shift of Zdy configuration
Figure 4-15: Equivalent electrical circuit of a linear 3-winding transformer
Figure 4-16: The model of a 12-pulse transformer
Figure 4-17: 24-Pulse-Diode-Rectifier with serial connections and Dzz configuration
Figure 4-18: 24-Pulse-Diode-Rectifier with serial connections and Zdy configuration
Figure 4-19: Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e, f)
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Figure 4-20: Primary and secondary winding currents of the 24-pulse transformer
Figure 4-21: DC link voltage and its harmonic spectrum (a, b), and dc link current and its harmonic spectrum, Idc = 710A, fC = 750Hz
Figure 4-22: 24-Pulse-Diode-Rectifier with independent connections: (a) Dzz configuration, and (b) Zdy configuration
Figure 4-23: Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e, f)
Figure 4-24: Primary and secondary winding currents of the 24-pulse transformer
Figure 4-25: DC link voltage and its harmonic spectrum, fC= 750Hz
Figure 4-26: DC link current and its harmonic spectrum, Idc = 471A, fC = 750Hz
Figure 5-1: Iterative design approach to the power semiconductor design
Figure 5-2: Iterative design approach to calculate the maximum converter output power SC,max and the semiconductor utilization (Tj = Tj,max, SS = const., fC = const.)
Figure 5-3: Iterative design approach to calculate the maximum carrier frequency (Tj = Tj,max, SS = const., SC = const.)
Figure 5-4: Iterative design approach to calculate the converter output power and losses (Tj = Tj,max, SS = const., f1Cb = const.)
Figure 5-5: Iterative design approach to calculate the maximum carrier frequency (Tj = Tj,max, SC = const., η = ηref ≈ const.)
Figure 5-6: The dc link voltage ripple ∆UC and the dc link stored energy EC as functions of the dc link capacitance for the 3L-NPC VSC (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos ϕ = 0.9, Udc = 6118V)
Figure 5-7: 24-pulse diode rectifier configurations (a) series configuration uses for the 3L-NPC VSC, (b) separate configuration uses for the9L-SCHB VSC
Figure 5-8: Voltage and power ranges of the selective medium voltage drives (Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-1: Converter semiconductor losses and efficiencies as functions of the phase current for the investigated output voltage classes (fC = 450Hz, ma = 1.15, cosϕ = 0.9): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-2: Converter semiconductor loss distribution at constant carrier frequency (fC = 450Hz, ma = 1.15, cosϕ = 0.9, Iph,rms,1 = 600A) (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-3: Harmonic spectrum of line-to-line output voltage at constant carrier frequency (fC = 450Hz, fo = 50Hz, ma = 1.15, f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC = 900Hz, f1Cb,4L-FLC = 1350Hz, f1Cb,5L-SC2LHB = 1800Hz, f1Cb,7L-SC2LHB = 2700Hz, f1Cb,9L-SC2LHB = 3600Hz) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A:
Figure 6-4: Converter semiconductor losses and efficiencies as functions of the carrier frequency for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC = 450Hz, Iph,rms,1 = 600A, ma = 1.15, cosϕ = 0.9) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-5: Converter semiconductor loss distribution at maximum carrier frequency (fo = 50Hz, ma = 1.15, cosϕ = 0.9, Iph,rms,1 = 600A, fC = 450Hz), (fC,3L-NPC = 450Hz, fC,3L-
Figure 6-6: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,2.3kV = 1760Hz f1Cb,4L-FLC,2.3kV = 750Hz f1Cb,5L-SC2LHB = 6340Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cosϕ = 0.9, Iph,rms,1 = 600A) (3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-7: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,3.3kV = 1270Hz, f1Cb,4L-FLC,3.3kV = 2370Hz, f1Cb,7L-SC2LHB = 7800Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cosϕ = 0.9, Iph,rms,1 = 600A) (4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 1.7kV/600A: FZ600R17KE3)
Figure 6-8: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,4.16kV = 1190Hz, f1Cb,4L-FLC,4.16kV = 2550Hz, f1Cb,9L-SC2LHB = 27600Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cosϕ = 0.9, Iph,rms,1 = 600A) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 1.7kV/600A: FZ600R17KE3)
Figure 6-9: Converter semiconductor losses as functions of the phase current for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5L-
Figure 6-14: Flying capacitor current (a) and voltage ripple (b) of a 3L-FLC VSC as functions of the modulation index and phase shift (Iph,rms,1 = 600A, fC,3L-FLC = 1200Hz, C = 770µF)
Figure 6-15: Flying capacitor current (a) and voltage ripple (b) of a 4L-FLC VSC as functions of the modulation index and phase shift (Iph,rms,1 = 600A, fC,4L-FLC = 1200Hz, C1,2 = 518µF)
Figure 6-16: Harmonic spectrum of line-to-line voltage at constant efficiency (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos ϕ = 0.9, Tjmax = 125°C, fC,3L-NPC-6.5kV = 450Hz, fC,3L-NPC-
Figure 6-17: Semiconductor loss distribution and relative installed switch power occurring at line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV at different switching frequencies of 450Hz, 750Hz, and 1050Hz (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos ϕ = 0.9, Tjmax = 125°C), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-18: The effective, average, and ripple capacitor current as a function of the modulation index and load angle in the 3L-NPC VSC according to Figure 3-6: (a-c) (idc2,eff,max/iph,peak = 85.6% at φ = ±180°, 0° and ma = 1.15), (idc2,avg,max/iph,peak = 80.3% at φ = 0° and ma = 1.15), (idc2,rip,max/iph,peak = 45.8% at φ = ±180°, 0° and ma = 0.6), and in the 9L-SC2LHB VSC according to Figure 3-39 (d-f).(idc21,eff,max/iph,peak = 68.7% at φ = ±180°, 0° and ma = 1.15), (idc21,avg,max/iph,peak = 57.5% at φ = 0° and ma = 1.15), (idc21,rip,max/iph,peak = 54.3% at φ = ±90°, and ma = 1.15), (iph,rms,1 = 600A, fC = 750Hz, fo = 50Hz)
Figure 6-19: (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-20: (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their
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harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-21: (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-22: (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-23: (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d): dc link current and its harmonic spectra, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-24: (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d): dc link current and its harmonic spectra in the 3L-NPC VSC, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-25: (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-26: (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-27: (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
Figure 6-28: (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
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List of Tables Table 2-1: Overview of available industrial medium voltage drives on the market
Table 2-2: Device rating and package types of typical MV power semiconductors
Table 3-1: Switch positions for each phase of the two-level VSC
Table 3-2: Conduction losses in the two-level VSC
Table 3-3: Switching losses in the two-level VSC
Table 3-4: Switch positions for one phase of the three-level NPC VSC
Table 3-5: Conduction losses in the 3L-NPC VSC
Table 3-6: Switching losses in the 3L-NPC VSC
Table 3-7: Switch positions for one phase of the three-level FLC VSC
Table 3-8: Conduction losses in the three -level FLC VSC
Table 3-9: Switching losses in the three-level FLC VSC
Table 3-10: Switch positions for the one phase of the four-level FLC VSC
Table 3-11: Switch positions for single-phase H-bridge cell
Table 3-12: Conduction losses in the single-phase full-Bridge converter
Table 3-13: Switching losses in the single-phase full-Bridge converter
Table 3-14: Quantities comparison of the SC2LHB VSC
Table 3-15: Switch positions for the 5L-SC2LHB VSC
Table 3-16: The output voltage levels of the 5L-SC2LHB VSC
Table 3-17: Number of redundancies in each phase voltage level of the 7L-SC2LHB VSC
Table 3-18: The output voltages and their corresponding levels of the 7L-SC2LHB VSC
Table 3-19: The output voltages and their corresponding levels of the 9L-SC2LHB VSC
Table 3-20: Switch positions for the 3L-H-Bridge converter
Table 3-21: Conduction losses in the 3L-H-Bridge converter
Table 3-22: Switching losses in the 3L-H-Bridge converter
Table 3-23: Comparison of power component requirements for multi-level topologies
Table 4-1: Fitting parameters and thermal resistances of medium voltage IGBTs/Diodes
Table 4-2: Thermal resistance of the IGBT module: FZ600R65KF1
Table 4-3: Harmonic current and their phase angles in 24-pulse transformers
Table 4-4: The necessary input data of the 12-pulse phase-shift transformer
Table 4-5: The secondary quantity parameters for the 24-pulse transformer with Zdy connection
Table 4-6: The designing parameters for the 24-pulse transformer with Zdy connection
Table 5-1: Critical operating points for the determination of the power semiconductor current ratings (stationary thermal design) for all considered topologies
Table 5-2: Converter data (Output phase current Iph,rms,1 = 600A)
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Table 5-3: Power semiconductor devices
Table 5-4: The converter specifications for medium voltage converters
Table 6-1: Power semiconductor design for Iph,rms,1 = 600A, fC = 450Hz / 1000Hz
Table 6-2: Maximum phase current and apparent converter output power for constant carrier frequency (Iph,rms,1 = 600A, ma = 1.15, cosϕ = 0.9)
Table 6-3: Maximum carrier frequency for constant apparent converter output power and constant installed switch power (Iph,rms,1 = 600A, ma = 1.15, cosϕ = 0.9)
Table 6-4: Maximum phase current and apparent converter output power for constant carrier frequency of the first carrier band and installed switch power (Iph,rms,1 = 600A, f1Cb = 450Hz / 1000Hz, ma = 1.15, cosϕ = 0.9)
Table 6-5: Converter voltage and semiconductor specifications for a constant converter power and carrier frequency (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA, fC = 450Hz, Tj,max = 125°C)
Table 6-6: Carrier and harmonic carrier band frequencies, capacity of flying capacitors and installed switch power for a converter efficiency of about 99% (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA)
Table 6-7: Power semiconductor design (Iph,rms,1 = 600A, ma = 1.15, cos ϕ = 0.9)
1. INTRODUCTION
The development of new high power semiconductors such as 3.3kV, 4.5kV, and 6.5kV Insulated Gate Bipolar Transistors (IGBTs), and 4.5kV to 5.5kV Integrated Gate Commutated Thyristors (IGCTs), and improved converter designs have led to a drastic increase of the market share of Pulse-Width-Modulated (PWM) controlled Voltage Source Converters (VSC) [21]. Despite a price reduction of Gate Turn-Off Thyristors (GTOs) by a factor of two to three over the last five years, also conventional GTO Voltage Source Converters and Current Source Converters (CSC) are increasingly replaced by PWM Voltage Source Converters with IGCTs or IGBTs in traction and industry applications [21].
Today the two-level Voltage Source Converter (2L-VSC) applying IGBTs is clearly the dominating converter topology in traction applications (low, medium, and high power propulsion) and the three-level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is mostly applied in industrial medium voltage converters. The 2L-VSC and the 3L-NPC VSC offer technical advantages like a simple power part, a low component count, and straightforward protection and modulation schemes. On the other hand, the hard-switching transients of the power semiconductors at high commutation voltage cause high switching losses and a poor harmonic spectrum which produces additional losses in the machine. Further problems are created by over-voltages in cables and machines as well as bearing currents due to the steep-switching transients [5], [21], [121].
Multi-level converters (MLCs) have been receiving attention in the recent years and have been proposed as the best choice in a wide variety of medium voltage (MV) applications [47]. They enable a commutation at substantially reduced voltages and an improved harmonic spectrum without a series connection of devices, which is the main advantage of a multi-level structure. Other advantages of these topologies are better output voltage quality, reduced electromagnetic interference (EMI) problems, and lower overall losses in some cases. However, today they have a limited commercial impact due to their disadvantages such as high control complexity and increased power semiconductor count compared to the 2L-VSC and the 3L-NPC VSC.
There is a large variety of power semiconductors (e.g. IGBTs, GTOs, IGCTs) and converter topologies (e.g. 2L-VSC, 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and SCHB VSCs). However, today there is no comparative analysis of the different converter topologies. Therefore, the objective of this thesis is a detailed comparison of state-of-the-art 2L-VSC, 3L-NPC VSC, and different multi-level VSCs (e.g. 3L-FLC VSC, 4L-FLC VSC, 5L-, 7L-, and 9L-SC2LHB VSCs) for medium voltage converters. On the basis of the application requirements, different ML converter structures are designed, simulated, and evaluated. The development of design tools based on state-of-the-art converters and semiconductors, which enable the dimensioning of power semiconductors, dc link capacitors, and transformers; are one major part of this thesis. Finally, the amount of active and passive components, the modulation, losses, and efficiency of aforementioned converters are calculated and compared.
The thesis is arranged in seven main chapters: This introduction is followed by an overview of medium voltage converter topologies, including medium voltage power semiconductors and modulations in chapter 2.
2 INTRODUCTION
Chapter 3 presents the basic structure and function of voltage source converter topologies. Based on the requirements for MV applications, advantages and disadvantages of the topologies are discussed.
One of the main parts of this thesis is the modelling and simulation of the different multi-level converters. The dimensioning and design of power semiconductors, dc link capacitors, and isolation transformers are developed in chapter 4.
The basic converter data for a converter comparison, including the IGBTs, modulation, switching frequency, and state of the art are described in chapter 5.
The comparison of the different converter topologies is performed in chapter 6 for 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and 5L-, 7L-, 9L-, and 11L-SCHB VSCs on the basis of the state-of-the-art 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs for 2.3kV, 3.3kV, 4.16kV, and 6kV medium voltage converters. As a result, the converter losses, the semiconductor loss distribution, the converter efficiency, harmonic spectrum analysis, and the installed switch power of the different converter topologies are compared in this chapter.
Finally, the conclusion and discussion are presented in chapter 7.
2. OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES
2.1. State of the Art in Medium Voltage Converters Multi-level voltage source converters have been studied intensively for high-power applications [44], [53], [87], [88]. Standard drives for medium voltage industrial applications have become available since the mid-1980s [27], [82], [83], [129]. These converters synthesize higher output voltage levels with a better harmonic spectrum and less motor winding insulation stress. However, the reliability and efficiency of the converter are reduced due to an increasing number of devices.
“Today there is a large variety of converter topologies for Medium Voltage Drives (MVD). For low and medium power industrial applications (e.g. S = 300kVA - 30MVA) the majority of the drive manufacturers offer different topologies of Voltage Source Converters: Two-Level Voltage Source Converters (2L-VSC) (e.g. Alstom), Three-Level Neutral Point Clamped Voltage Source Converters (3L-NPC VSC) (e.g. ABB, Alstom, Siemens), Four-Level Flying Capacitor Voltage Source Converters (4L-FLC VSC) (e.g. Alstom: SYMPHONY [80]) and Series Connected H-Bridge Voltage Source Converters (SCHB VSC) (Robicon [81], [139]). One manufacturer (Allen Bradley) still offers self-commutated current source inverters (CSI). While 4.5kV, 6kV and 6.5kV IGCTs are mainly used in 3L-NPC VSCs and CSIs respectively; 2.5kV, 3.3kV, 4.5kV and 6.5kV High Voltage IGBTs (HV-IGBTs) are applied in 2L-VSCs, 3L-NPC VSCs and 4L-FLC VSCs. In contrast, 1.2kV and 1.7kV Low Voltage IGBTs (LV-IGBTs) are usually applied in SCHB VSCs [94]”.
Among the high-power multi-level converters, three topologies have been successfully implemented as standard products for medium voltage industrial drives: the Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) [82], [83], the Four-Level Flying Capacitor Voltage Source Converters (4L-FLC VSC) [80], and the Series Connected H-Bridge Voltage Source Converters (SCHB VSC) [27], [129].
In medium voltage applications, the 3L-NPC topology has been accepted by several large manufacturers. ABB is using this topology in both their ACS 1000 [83] and ACS 6000 series, in a voltage and power range of 2.3kV-4.16kV and 315kVA-27MVA [154]. Siemens’ SIMOVERT MV [155] is also utilising this topology with output voltages from 2.3kV to 6.6kV and a power range from 660kVA to 9MVA. Not only European but also Asian vendors, such as Mitsubishi, employ the 3L-NPC converter [48].
The NPC topology uses high-voltage blocking devices with a relatively low switching frequency capability. This topology has a simple circuit but it needs a large inductive-capacitive (LC) output filter to operate standard motors.
The 4L-FLC VSC is attractive if a very high switching frequency, a low harmonic distortion, and a small output filter or a high output voltage is required [25].
The SCHB topology uses low-voltage blocking devices (e.g. 1700V IGBTs) with a high switching frequency capability. It typically consists of three to six equal H-bridge cells per phase, which results in a seven- to thirteen-level output voltage waveform. An input isolation transformer feeds each of the H-bridges via its own three-phase winding and full-bridge diode-
4 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES
rectifier. To obtain a high pulse number at the primary side, secondary transformer windings in star, delta, zigzag, and combinations are used. This topology has excellent utility grid current and output voltage waveforms. However, the cost of the complex input transformer and the high number of semiconductor devices with their control equipment are its drawbacks.
The disadvantages of both topologies can be limited by using a hybrid asymmetric multi-level converter which is constructed by combining the SCHB with the NPC topologies [133], [134]. This combination produces more output voltage levels with the same number of components than a symmetric multi-level converter. The first H-bridge cells of each phase in the SCHB topology are replaced by a leg of the NPC converter. Although an H-bridge cell and a leg of the NPC converter provide the same output voltage level, the hybrid asymmetric multi-level topology requires a smaller number of separate dc sources and H-bridge cells for the same output voltage levels [85], [86]. This leads to a further simplification of the feeding transformer and rectifiers [84]. This topology can be operated with a low or high switching frequency for high- or low-voltage applications. However, the need for a complex input transformer remains and its control would be complicated due to its structure, so that it is not commercially offered on the market.
Table 2-1 summarizes the available industrial medium voltage drive applications offered by drive manufactures [28]. The voltage source converter topology applying IGBTs and IGCTs are offered by the majority of manufactures. The medium voltage drives cover power ratings from 0.2MW to 40MW at the medium voltage level of 2.3kV to 13.8kV [9], [28]. These drives are used in various applications such as traction [21], electric power, and other industries [35]. The medium voltage traction converters are mostly fed by a single-phase ac line using a low-frequency transformer (e.g. 15kV 216 3 Hz or 25kV 50Hz) [21], [38], [39]. The feeding of
some traction converters by dc mains is also possible, but due to the large variations of the dc voltages of -30% to +40%, such applications are complicated [21].
Figure 2-1 represents the most important power converters on the market and their rated voltages and powers today [14], [28].
Table 2-1 Overview of available industrial medium voltage drives on the market [28], [75]
Manu-facturer Type Power
(MVA) Voltage
(kV) Topology Semiconductor
Robicon Perfect Harmony 0.3-31 2.3-13.8 ML-SCHB-VSC LV IGBT Allen Bradley Power Flex 7000 0.15-6.7 2.3, 3.3,
Electric MV-GP Type H 0.45-7.5 3.3, 4.16 ML-SCHB-VSC IGBT
OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES 5
Figure 2-2 illustrates two examples of medium voltage drives: Figure 2-2a shows a medium voltage drive using an IGBT-based 3L-NPC inverter (SIMOVERT [9]). The standardized output power range extends for motors from about 0.2MW up to more than 7MW [150]. Figure 2-2b shows a 4.16kV, 7.5MW SCHB inverter with five identical IGBT power cells which generate 21 levels at the line-to-line output voltage (ASI Robicon [9]).
Figure 2-1 Application ranges of commercially available power semiconductors [14], [28]
Figure 2-2 IGBT-based inverter fed medium voltage drives: (a) 3L-NPC, (b) SCHB [9], [75]
(a) Cabinet of Siemens (SIMOVERT MV) (b) Cabinet of ASI Robicon (Perfect Harmony)
6 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES
2.2. State of the Art in Medium Voltage Power Semiconductors Recent technology advances in power electronics have been made by improvements in controllable power semiconductor devices. Figure 2-3 and Figure 2-4 summarize the most important power semiconductors on the market and their rated voltages and currents today [14], [21]. The device characteristics for medium voltage power semiconductors are shown in Table 2-2 [28].
Metal Oxide Semiconductor Field Effect Transistors (MOSFET) and IGBTs have replaced Bipolar Junction Transistors (BJT) almost completely. A remarkable development in MOSFETs took place during the last years. Nowadays MOSFETs are available up to a maximum switch power of about 100kVA [21].
Various new concepts of MOS-controlled thyristors such as the MOS-controlled thyristor (MCT) and the MOS turn-off thyristor (MTO) have been presented but they do not have any commercial applications.
Conventional GTOs are available with a maximum device voltage of 6kV in traction and industrial converters (Table 2-2) [21], [28]. The high on state current density, the high blocking voltages, and the possibilities to integrate an inverse diode are considerable advantages of these devices. However, the requiring of bulky and expensive snubber circuits [92], [93] as well as the complex gate drive are the reasons that GTOs are being replaced by IGCTs and Gifts [21], [28]. Like GTOs, IGCTs are offered only as a presspack device. The symmetrcial IGCT is offered by Mitsubishi with a maximum device voltage of 6.5kV (Table 2-2) [21], [28]. An increase of the blocking voltage of IGCTs and inverse diodes to 10kV is technically possible today [21].
Due to the thyristor latching, a GTO structure offers lower conduction losses than an IGBT of the same voltage class. To improve the switching performance of classical GTOs, gate-commutated thyristors (GCTs) with a very little turn-off delay (about 1.5µs) have been developed [90], [91]. New asymmetric GCT devices up to 10kV with peak controllable currents up to 1kA have been manufactured but only those devices with 6kV and 6kA are commercially available.
IGBTs were introduced on the market in 1988. IGBTs from 1.7kV up to 6.5kV with dc current ratings up to 3kA are commercially available today (Table 2-2) [21], [28]. They have been optimized to satisfy the specifications of the high-power motor drives for industrial and traction applications. They are mainly applied in a module package due to the complex and expensive structure of an IGBT presspack [28].
In IGBT modules, multiple IGBT chips are connected in parallel and bonded to ceramic substrates to provide isolation. Both IGCTs and IGBTs have the potential to decrease the cost of systems and to increase the number of economically valuable applications as well as the performance of high-power converters, compared to GTOs, due to a snubberless operation at higher switching frequencies (e.g. 500-1000Hz).
Figure 2-5 represents the typical converter voltage as a function of power ratings for both IGBT and IGCT applications [28], [30], [31]. It can be seen that LV-IGBT modules are commercially available with a maximum device voltage of 1700V on the entire low-voltage drive market (i.e. up to 690V). On the other hand, MV-IGBT modules enable converter designs in a voltage range from 1kV up to 7.2kV with a power range from 200kVA up to 7MVA (Figure 2-4) [28]. MV-IGBT modules have replaced GTOs in recent traction applications.
“IGBT presspacks are applied mainly in self-commutated High Voltage Direct Current (HVDC) converters (e.g. HVDC light) where a redundant converter design is a main
OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES 7
requirement and each converter switch position consists of a series connection of many IGBTs (e.g. n ≥ 10) [28].”
Table 2-2 Device rating and package types of typical MV power semiconductors [28]
Figure 2-3 Classification of state-of-the-art power semiconductors [21]
Power Semiconductors
Silicon CarbideSilicon
Diodes Transistors Thyristors Diodes Transistors
Schottky
PIN
Double(PIN)
BJT
MOSFET
IGBT
GTO
IGCT
GCT
MCT
MTO
Schottky
JBS
PIN
MOSFET
Low importance on the market today
Power Semiconductors Manufacturer Voltage Ratings Current Ratings Case
IGCTs enable converter designs in the high power range from 5MVA up to 100MVA in a voltage range of 2.3kV to 15kV. The majority of applications are industrial converters and drives as well as interties, dynamic voltage restorers, and energy storage systems [28].
Figure 2-4 Power range of commercially available power semiconductors [14], [21]
Figure 2-5 Application ranges of IGBTs and IGCTs [28], [30], [31]
Ull
3. BASIC STRUCTURE AND FUNCTION OF MULTI-LEVEL VOLTAGE SOURCE CONVERTER TOPOLOGIES
This chapter describes the basic structure and function of Multi-level VSC topologies. The principle of operation that includes the structure, switching states, and modulation methods are discussed for the 2L-VSC, 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, 9L-SC2LHB VSC, and the hybrid VSC.
3.1. Two-Level Voltage Source Converter (2L-VSC)
3.1.1. Structure of Two-Level Voltage Source Converter The three-phase 2L-VSC consists of three legs, one for each phase, as shown in Figure 3-1. Each converter leg consists of two active switches and two freewheeling diodes in parallel with each switch. The output of each leg of the three-phase converter depends only on the dc link voltage Udc and the switch state. The output voltage is independent of the output load current since one of the two active switches or freewheeling diodes in a leg is always on at any instant. Therefore, the converter output voltage is independent of the direction of the load current.
Figure 3-1 Two-Level Voltage Source Configuration
3.1.2. Switch States and Commutations As shown in Figure 3-1, the three-phase two-level VSC contains six unidirectional active switches having inverse diodes. Each ac terminal of the converter (a, b, or c) can be connected to the positive dc rail "+" or the negative dc rail "-". Thus, the number of different converter switch states calculates to
32 8phswn N= = = (3-1)
with N being the number of voltage levels in the dc link and ph being the number of phases.
S1c
idc
DT1aT1a
T2a
a
DT2a
DT1bT1b
T2b
b
DT2b
DT1cT1c
T2c
c
DT2c
C2
C1
Uc2
Uc1
M
-
+
UdcUaM
n
Uab Ubciph,a
10 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The switch positions for two possible states of each phase leg are given in Table 3-1, where 1 and 0 denote the on- and off state of the switch. Figure 3-2a depicts the eight active inverter voltage vectors for the three-phase two-level VSC, where [0 0 1] means that S1a, S1b are switched off and S1c is switched on.
Figure 3-2 Switch states: (a) conduction paths, (b) commutations and switching losses of the
2L-VSC
a b c
[0 0 1]
a b c
[1 0 0]
a b c
[1 1 0]
a b c
[1 0 1]
a b c
[0 1 1]
a b c
[0 1 0]
a b c
[1 1 1]
a b c
[0 0 0]
(a)
DT1aT1a
T2a
a
DT2a
C2
C1
M
-
+
DT1aT1a
T2a
a
DT2a
C2
C1
M
-
+
2dcU
2dcU
2dcU
2dcU
(b)
DT1aT1a
T2a DT2a
C2
C1
M
-
+
DT1aT1a
T2a DT2a
C2
C1
M
-
+
2dcU
2dcU
2dcU
2dcU
(c)
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 11
Table 3-1 Switch positions for each phase of the two-level VSC
The current paths for positive and negative phase currents iph are depicted in Figure 3-2b. In any switch state, one semiconductor lies within the current path. It should be noted that all switches and diodes of the two-level VSC are stressed by Udc. Assuming a sinusoidal phase current, the maximum switch/diode current is the maximum phase current phi . These parameters determine the rating of the main semiconductors.
Switching losses are created by the commutation processes between the different switch states. Only turn-on and turn-off losses of active switches and recovery losses of diodes are considered. Turn-on losses of diodes are usually small so that they can be neglected [1]. The distribution of the switching losses and the conduction losses are summarized in Table 3-2 and Table 3-3 respectively.
For a positive phase current iph > 0, the commutation (+ → –) is initiated by the turn-off of T1x and the current forced from T1x to DT2x (x = a, b, c). The situation is visualized in Figure 3-8c, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. In contrast, the commutation (– → +) is initiated by the turn-off of D2x and the current forced from DT2x to T1x.
For a negative phase current iph < 0, the commutation (+ → –) is initiated by the turn-off of DT1x and the current forced from DT1x to T2x. In contrast, the commutation (– → +) is initiated by the turn-off of T2x and the current forced from T2x to DT1x, as shown in Figure 3-8c.
Table 3-2 Conduction losses in the two-level VSC
Table 3-3 Switching losses in the two-level VSC
3.1.3. Sine-Triangle Modulation The purpose of PWM three-phase converters is to shape and to control the three-phase output voltages in magnitude and frequency with an essentially constant input voltage Udc. To obtain balanced three-phase output voltages in a three-phase PWM, the same triangular voltage
12 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
waveform triU is compared with three control voltage waveforms ( )con,a con,b con,cU , U , U that are 120° out of phase.
In order to generate the switching signals, three control signals are compared with a repetitive switching frequency triangular waveform, as shown in Figure 3-3a. The frequency modulation ratio fm and the amplitude modulation ratio am of a PWM are defined as
trif
n
fmf
= (3-2)
1con ,a
tri
Um
U= (3-3)
where 1con,U denotes the peak value of the fundamental component of the reference voltage.
For a sine-triangle modulation the linear modulation range is limited to values of 1am ≤ . By adding a third harmonic with one-sixth of the fundamental amplitude, it can be expanded to its theoretical maximum of ma = 1.155 [73]. Thus, the reference control voltage per phase is
( ) ( )1 1 11 36con,x con,
ˆU ( t ) U sin w t sin w t⎡ ⎤= ⋅ +⎢ ⎥⎣ ⎦ (3-4)
In order to trigger the switches, the following algorithm can be used:
( ) ( )1 2 2dc
con,x tri x x xmUU U S on S off U x a,b,c> ⇒ = = ⇒ = = (3-5)
( ) ( )1 2 2dc
con,x tri x x xmUU U S off S on U x a,b,c< ⇒ = = ⇒ = − = (3-6)
Since the two switches are never off simultaneously, the output voltage UxM fluctuates between two values (Udc/2 and –Udc/2). The gating signals (Vg1,x and Vg2,x) and switching sequence according to Figure 3-1 are depicted in Figure 3-3b (for 15fm = ).
3.1.4. Output Waveforms and Spectrum
The following equations will be very helpful to obtain the line-to-line voltages (Uab, Ubc and Uca) and line-to-neutral voltages (Uan, Ubn and Ucn) respectively. For all investigations in this thesis, a load with a floating star point is assumed.
ab aM bMU U - U = (3-7)
an aM nMU U - U = (3-8)
where the common mode voltage UnM is calculated as
( )13nM aM bM cMU U U U = + + (3-9)
It should be noted that the same value of the average dc component exists in the output voltages of any one of the legs, which are measured with respect to the negative dc rail "-". These dc components are suppressed in the line-to-line voltages, as shown in Figure 3-3d. The phase-midpoint output voltage waveform (UaM, UbM, and UcM) and the common mode voltage are depicted in Figure 3-3c and Figure 3-3e respectively. The common mode voltage can assume the voltage levels of ±Udc/2 and ±Udc/6.
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 13
Figure 3-3 Voltage waveforms of the 2L-VSC: (a) control signals Ucon, x and triangular signal
Utri, (b) gating signals in phase a, (c) phase-midpoint output voltage UaM, (d) line-to-line output voltage Uab, (e) common mode voltage UnM
0 90° 180° 270° 360°
Udc / 2
-Udc / 2
0
Udc
-Udc
0
Udc
-Udc
0
Utri Ucon, a Ucon, b Ucon, c
1
1
0
0
Vg1, a
Vg2, a
(a)
(b)
(c)
(d)
UaM
Uab
(e)Udc / 2
-Udc / 2
0
UnM
-Udc / 6
Udc / 6
14 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
In order to eliminate even harmonics, the frequency modulation ratio fm should be odd. The odd harmonics in the phase-midpoint voltages are the same as the output of any one of the legs, centred around the switching frequency and its multiples (mf, 2mf, ...), as shown in Figure 3-4a.
Various harmonics in the line-to-line voltage (Uab, Ubc and Uca) are suppressed due to the phase difference between the fm harmonic in the output voltage of any one of the legs, as shown in Figure 3-4b.
Figure 3-4 Harmonic spectrum of the 2L-VSC: (a) phase-midpoint output voltage, (b) line-to-
line output voltage
3.2. Diode Clamped Voltage Source Converter (DC VSC)
3.2.1. Structure A type of a voltage source converter configuration, which is important for high-power applications, is the so-called diode clamped (DC) converter. The diode-clamped converter provides multiple voltage levels through the connection of the phases to a series bank of capacitors. According to the original invention [127], the concept can be extended to any number of levels by increasing the number of capacitors. Early descriptions of this topology were limited to three levels [37], where two capacitors were connected across the dc bus resulting in one additional level. The additional level was the neutral point of the dc bus; hence, the terminology NPC converter was introduced [37]. However, with an even number of voltage levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is sometimes applied [41]. Due to capacitor voltage balancing and also high voltage stress on the clamping diodes with a number of levels larger than three, the diode-clamped converter implementation has been mostly limited to three levels [17], [122], [123]. In this case the converter is usually called Three-Level Neutal Point Clamped Voltage Source Converter (3L-
1 mf 2mf 3mfHarmonic Order
1 3 mf 2mf 3mf
0
0.2
0.4
0.6
0
0.2
0.4
0.6
0.8
1
( )ab h
dc
UU
( )aM h
dc
UU
(a)
(b)
Har
mon
ic M
agni
tude
(p.u
.)H
arm
onic
Mag
nitu
de(p
.u.)
mf = 15, ma = 1.15
mf = 15, ma = 1.15
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 15
NPC VSC).
One phase leg consists of 2(N-1) active switches and (N-1) (N-2) clamping diodes, where N is the number of voltage levels shown in Figure 3-5 [122]. The total dc bus voltage Udc is distributed across the dc capacitors C1, C2, ..., C(N-1). Hence, an output voltage of –Udc / (N-1), ..., Udc / (N-1) is possible at the output [47].
Figure 3-5 One-phase N-Level Neutral Point Clamped Converter [122]
3.2.1.1. Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) The topology of the three-level neutral point clamped (diode-clamped) converter is presented in Figure 3-6. It contains 12 unidirectional active switches having inverse diodes and 6 neutral point clamp diodes. The switches 1x 2 xS ,S are named “outer switches” ( outS ) and the remaining switches 1 2x xS ,S are designated “inner switches” ( inS ). The group of NPC-diodes is referred to as 2 1x xD ,D . This converter has a zero dc voltage centre point "M1", which is switchable to the phase outputs, thereby creating the possibility of switching each converter phase leg to one of three voltage levels. The major benefit of this configuration is that, while there are twice as many switches as in the two-level converter, each of the switches must block only one-half of the dc link voltage "Udc/2" [7]. However, one problem that does not occur in a two-level converter is the need to ensure voltage balance across the two series-connected capacitors making up the dc link. One solution is to simply connect each of the capacitors to its own
Udc
aiph,a
S1a
S2a
S(N-1)a
S(N-2)a
S(N-3)a
1( N - )aS
2( N - )aS
D(N-1)a
D(N-2)a
D(N-3)a
idc(N-1)
idc(N-2)
idc(N-3)
ic1
ic(N-1)
ic(N-2)
ic(N-3)
Mo
M1
M(N-1)
M(N-2)
M(N-3)
C(N-1)
C(N-2)
C(N-3)
C1
3( N - )aS
2aS
1aS
idc(N-4)
ic(N-4)
M(N-4)
idc1
D2a
16 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
isolated dc source (for example, the output of a diode bridge fed from a secondary transformer) [7], [124]. The other method is to balance the two capacitor voltages by feedback control [7], [124], [125].
Figure 3-6 Three-phase Three-Level Neutral Point Clamped Converter
3.2.1.1.1. Switch States and Commutations
In order to produce three levels, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time [37]. In summary, each phase node (a, b, or c) can be connected to any node in the capacitor bank (M0, M1, and M2). Thus, the number of different converter switch states calculates to
33 27phswn N= = = (3-10)
with N being the number of voltage levels in the dc link and ph being the number of phases.
Connection of the a-phase to junctions M0 and M2 can be accomplished by switching both transistors T1a and T2a either off or on. These states are the same as the two-level inverter, yielding a phase voltage of UxM1 = Udc/2 or UxM1 = -Udc/2 assuming UC2 = UC1 = Udc/2. The connection to the junction M1 is accomplished by gating T1a on and T2a off. In this representation, the labels T1a and T2a are used to identify the transistors as well as the transistor logic (1 = on and 0 = off). Since the transistors are always switched in pairs, the complement transistors are labelled 1aT and 2aT accordingly. In a practical implementation, some dead time is inserted between the transistor signals and their complements meaning that both transistors in a complementary pair may be switched off for a small amount of time during a transition. However, for this discussion here the dead time will be ignored.
From Figure 3-6 it can be seen that, with this switching state, the a-phase current iph,a will flow into the junction through diode D1a if it is negative, or out of the junction through diode D2a if the current is positive. According to this description, the switch positions for three possible states of each phase leg are given in Table 3-4.
The current paths for positive and negative phase currents iph are depicted in Figure 3-7. In zero state, the direction of iph determines whether the upper or lower path of the neutral tap is
Udc
DT2aT2a
DT1aT1a
T2a
T1a
D2a
D1a
a
DT2bT2b
DT1bT1b
T2b
T1b
D2b
D1b
b
DT2cT2c
DT1cT1c
T2c
T1c
D12
D1c
c
C2
C1
M1
Uc2
Uc1
idco
idc1
idc2M2
M0
iph,a
S2c
Uab Ubc
n
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 17
utilized. Therefore, both 1xS and 2xS have to be turned on in zero state "0" to provide an open path in case the phase current reverses. In any switch state, two semiconductors in series lie within the current path, either two active switches or two diodes for the states positive "+" and negative "-". It should be noted that each of the switches must block only one-half of the dc link voltage Udc/2 assuming sinusoidal currents. The maximum switch/diode current is the maximum phase current phi . These parameters condition the rating of the main semiconductors. The distribution of the conduction losses is summarized in Table 3-5.
Table 3-4 Switch positions for one phase of the three-level NPC VSC
Figure 3-7 Conduction path of the Three-Level Neutral Point Clamped Converter
Table 3-5 Conduction losses in the 3L-NPC VSC
Switching losses are created by the commutation processes between the different switch states. For a positive phase current iph > 0, the commutation from "+" towards "-" (+ → 0 → –) is named “forced commutation”. The contrary natural commutation (– → 0 → +) realizes a positive output power gradient. They are initiated by an active turn-on transient.
For the following discussion of commutations, a positive phase current iph > 0 is assumed. Only turn-on and turn-off losses of active switches and recovery losses of diodes are
2xS
1xS
2xS
1xS
2xD
1xD
2dcU
2dcU 2xS
1xS
2xS
1xS
2xD
1xD
2dcU
2dcU 2xS
1xS
2xS
1xS
2xD
1xD
2dcU
2dcU
State 1xT 1T xD 2xT 2T xD 1xT 1T xD 2xT 2T xD 1xD 2xD Positive phase current
18 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
considered. For a positive phase current iph > 0, the commutation (+ → 0) is initiated by the turn-off of T2x and the current is forced from T2x to D2x. After a dead time (to ensure that T2x has completely turned off), 2xT is turned on. The switches T1x and 1xT stay on and off respectively. Only two switches and diodes are involved in this commutation: T2x and D2x. Essential turn-off losses occur in T2x. Though the switch 2xT is turned on, it does not experience losses since it does not take over any current after the commutation.
For the reverse commutation (0 → +), all switching transitions take place in the reverse order. 2xT is turned off first, followed by turning on T2x after the dead time. Turning off 2xT does not
affect the phase current. It only returns to the positive rail after the turn-on of T2x. Recovery losses occur in D2x, and T2x experiences turn-on losses. The situation for this pair of commutations is visualized in Figure 3-8a, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled.
Four devices are involved in the commutation (0 → –) (Figure 3-8b). It is started by the active turn-off of the switch T1x, forcing the current from its path through D2x and T1x to 1T xD and
2T xD . 2xT has already been in the on state before; 1xT is turned on after a dead time. T1x faces turn-off losses.
Figure 3-8 Commutations and switching losses in the 3L-NPC VSC: (a) and (b) for positive
load current, (c) and (d) for negative load current
2 xS
1xS
2xS
1xS
2 xD
1xD
2dcU
2dcU
2 xS
1xS
2xS
1xS
2 xD
1xD
2dcU
2dcU
2 xS
1xS
2xS
1xS
2 xD
1xD
2dcU
2dcU
2 xS
1xS
2xS
1 xS
2 xD
1xD
2dcU
2dcU
on
off
EE
on
off
EE
on
off
EE
on
off
EE
recE
recE
recE
recE
(a) (b)
(c) (d)
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 19
Although the diode D2x in series with T1x is turned off too, it does not experience notable recovery losses since it does not take over voltage after the commutation. Again, for the reverse commutation (– → 0), all switching transitions take place in the reverse order. 1xT is turned off, and T1x is turned on after a dead time. After triggering T1x, the phase current commutates from 1T xD and 2T xD back to D2x and T1x. Both diodes in series 1T xD and 2T xD are turned off, but only 1T xD takes over blocking voltage.
Thus, only 1T xD experiences recovery losses. T1x faces turn-on losses. This situation is depicted in Figure 3-8b. The commutations at negative phase current are illustrated in Figure 3-8c and Figure 3-8d.
The distribution of the switching losses is summarized in Table 3-6. It is important to note that all commutations in the NPC VSC can be explained by the basic commutation cell, comprising one active switch and one diode.
Table 3-6 Switching losses in the 3L-NPC VSC
3.2.1.1.2. Sine-Triangle Modulation
To obtain balanced three-phase output voltages, the converter is controlled by a PWM technique. The reference control voltage per phase is
( ) ( )1 1 11 36con,x con,
ˆU ( t ) U sin w t sin w t⎡ ⎤= ⋅ +⎢ ⎥⎣ ⎦ (3-11)
where 1con,U denotes the peak value of the desired fundamental component of the reference voltage.
In order to generate the switching signals, two triangular voltage waveforms tri ,upU and tri ,lowU are compared with three control voltage waveforms that are 120° out of phase (which is drawn for 15fm = ), as shown in Figure 3-9a.
In order to trigger the switches, the following algorithm can be used
( )
( )( )
1
1
1
2 1
2 1
, 2
, 2
0
dccon,x tri ,up x x xM
dccon,x tri ,low x x xM
xM
UU U S on S on U
UU U S on S on U
else U x a,b,c
⎧ > = = ⇒ =⎪⎪⎪ < = = ⇒ = −⎨⎪⎪ ⇒ = =⎪⎩
(3-12)
The positive half wave of the desired sinusoid is generated by switching the respective phase leg
State 1xT 1T xD 2xT 2T xD 1xT 1T xD 2xT 2T xD 1xD 2xD Positive phase current
0+ ↔ × × 0 ↔ − × ×
Negative phase current 0+ ↔ × ×
0 ↔ − × ×
20 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
between the positive "+" and zero "0" states, and the negative half wave is generated by switching between the zero "0" and negative "-" states. The average switching frequency per device equals half the carrier frequency visible at the output.
Figure 3-9 Voltage waveforms of the 3L-NPC VSC: (a) control signals Ucon, x and triangular
signals Utri,up and Utri,low, (b) gating signals in phase a, (c) phase-midpoint output voltage UaM1, (d) line-to-line output voltage Uab, (e) common mode voltage UnM1
0 90° 180° 270° 360°
Udc / 2
-Udc / 2
0
Udc
-Udc
0
Udc
-Udc
0
Utri,up Ucon, a Ucon, b Ucon, c
1
10
0
Vg1, a
Vg2, a
(a)
(b)
(c)
(d)
UaM1
Uab
Udc / 2
-Udc / 2
0
(e)
Utri,low
UnM1
Udc / 2
-Udc / 2
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 21
The output voltage fluctuates between three values (Udc/2, 0, and –Udc/2). The gating signals and switching sequence according to Figure 3-6 are depicted in Figure 3-9b.
The output voltage waveforms of the three-phase 3L-NPC VSC according to Figure 3-6 are depicted in Figure 3-9. The line-to-line voltages of the three-level converter, e.g.
1 1ab aM bMU U - U= (3-13)
comprise five voltage levels, viz. +Udc, +Udc/2, 0, -Udc/2, -Udc (see Figure 3-9d).
The connection of two considered phases to the opposite dc rails gives rise to the maximum line-to-line voltage of ±Udc. The intermediate voltage levels are generated by connecting one phase to neutral point M1, whereas both phases switched to the same dc terminal create a zero voltage.
The comparison of the line-to-line voltage waveform of Figure 3-9d with that of a two-level converter clearly reveals the superior output voltage quality of the 3L-NPC VSC. The steps in the line-to-line voltage are reduced to Udc/2, compared to Udc for the two-level converter. Moreover, the reduction of the commutation voltage to Udc/2 yields lower switching losses for every single commutation [3].
The common mode part of the phase voltages drops between load star point "n" and converter neutral point "M1". The common mode voltage depicted in Figure 3-9e is calculated as
( )1 1 1 1
13nM aM bM cMU U U U= + + (3-14)
and the line-to-neutral voltage shown in Figure 3-9c is as follows
1 1an aM nMU U - U= (3-15)
The line to neutral voltage consists of nine voltage levels, viz. ±2Udc/3, ±Udc/2, ±Udc/3, ±Udc/6, and 0.
Figure 3-10 Harmonic spectrum of the 3L-NPC VSC: (a) phase-neutral point output voltage,
(b) line-to-line output voltage
1 mf 2mf 3mfHarmonic Order
1 3 mf 2mf 3mf
10-3
10-3
100
( )1aM h
dc
U
U
( )ab h
dc
UU
100
(a)
(b)
Har
mon
ic M
agni
tude
(p.u
.)H
arm
onic
Mag
nitu
de(p
.u.)
mf = 15, ma = 1.15
mf = 15, ma = 1.15
22 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The common mode voltage can assume the voltage levels of ±Udc/2, ±Udc/3, ±Udc/6, and 0. However, the maximum common mode voltage arises from the connection of all three phases to either the positive or the negative dc link.
The odd harmonics in the line-to-neutral voltages are centred around a switching frequency and its multiples ( f f fm ,2m ,3m ,...), as shown in Figure 3-10a. Some dominant harmonics are suppressed in the line-to-line voltage (Uab, Ubc and Uca), as shown in Figure 3-10b.
3.3. Flying Capacitor Voltage Source Converter (FLC VSC)
3.3.1. Flying Capacitor Converter Structure
Another fundamental multi-level topology, the flying capacitor converter, involves a series connection of capacitor switching cells [44]. This topology has several unique and attractive features when compared to the diode-clamped converter. One feature is that added clamping diodes are not needed. Furthermore, the flying capacitor converter has a switching redundancy within the phase, which can be used to balance the flying capacitors so that only one dc source is needed.
Traction converters (e.g. T13 locomotive [45]) and industrial medium voltage converters (e.g. SYMPHONY [45], [80]) are typical applications of this topology.
One phase leg consists of 2(N-1) active switches and (N-2) flying capacitors, with N being the number of level voltage waveforms UxM shown in Figure 3-11 [47].
Figure 3-11 The generalized N-Level Flying Capacitor Converter [122]
Cell 1
Udc aiph,a
S1a
S2a
S3a
1aS
2aS
ic(N-2),a
ic1,a
C(N-2)a C2a C1a
3aS
ic2,a
dcU2
dcU2
M
S(N-1)a
S(N-2)a
2( N )aS −
1( N )aS −
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 23
3.3.1.1. Three-Level Flying Capacitor Voltage Source Converter (3L-FLC VSC) The topology of the three-level flying capacitor converter is presented in Figure 3-12. It contains 12 unidirectional active switches having inverse diodes and 3 flying capacitors. The general concept of operation is that each flying capacitor is charged to one-half of the dc voltage. It can be connected in series with the phase to add or subtract this voltage.
In order to produce three levels, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time. In this representation, the labels T1a and T2a are used to identify the transistors as well as the transistor logic (1 = on and 0 = off). Since the transistors are always switched in pairs, the complement transistors are labelled 1aT and
2aT accordingly.
Table 3-7 shows the switch positions for each phase leg. In comparison to the three-level diode clamped converter, an extra switching state is possible. In particular, there are two transistor states which make up the zero state. Considering the direction of the a-phase flying capacitor current ic1,a for the redundant states, a decision can be made to charge or discharge the capacitor, and the capacitor voltage can therefore be regulated to its desired value by operating the switches within the phase.
Due to two switch states that produce the same output voltage but different current directions through the flying capacitor, the capacitors can be balanced regardless of the load current.
Table 3-7 Switch positions for one phase of the three-level FLC VSC
24 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The current paths for positive and negative phase currents iph are depicted in Figure 3-13. For positive and negative phase currents, either both 1 2x xS ,S or both 1 2x xS ,S , have to be turned on in state "0". In any switch state, two semiconductors in series lie within the current path, either two active switches or two diodes for the states "+" and "-". Like the 3L-NPC, each switch must block only one-half of the dc link voltage Udc/2. The distribution of the conduction losses is summarized in Table 3-8.
Switching losses are created by the commutation processes between the different switch states.
Figure 3-13 Conduction path of the Three-Level Flying Capacitor Converter
Table 3-8 Conduction losses in the three-level FLC VSC
State 1xT 1T xD 2xT 2T xD 1xT 1T xD 2xT 2T xD Positive phase current
“+” × × × × “0” × ×
“-” × × Negative phase current
“+” × × × × “0” × ×
“-” × ×
T1x
T2x
C1x
DT2x
DT1x
dcU2
dcU2
M1xT
2xT
(d)
T1x
T2x
C1x
DT2x
DT1x
dcU2
dcU2
M
1xT
2xT
(b)
T1x
T2x
1xT
2xT
C1x
DT2x
DT1x
dcU2
dcU2
M
(a)
T1x
T2x
C1x
DT2x
DT1x
dcU2
dcU2
M
1xT
2xT
(c)
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 25
For a positive phase current iph > 0, the commutation (+ → 0) is initiated by the turn-off of T1x. After a dead time (to ensure that T1x has completely turned off), 1xT is turned on and the current is forced from T1x to 1xD . The switches T2x and 2xT stay on and off respectively. Essential turn-off losses occur in T1x. For the reverse commutation (0 → +), all switching transitions take place in the reverse order. 1xT is turned off first, followed by the turn-on of T1x after the dead time. The situation for this pair of commutations is visualized in Figure 3-14a, where the commutation (+ → 0) is marked bold and the reverse commutation (0 → +) is marked with a dashed line. The loss devices are encircled.
The commutation (0 → –) is started by the active turn-off of the switch T2x, forcing the current to 2T xD . 1xT has already been in the on state and T2x faces turn-off losses. Again, for the reverse commutation (– → 0), all switching transitions take place in the reverse order. 2xT is turned off and T2x turned on after a dead time. After triggering T2x, the phase current commutates from
2T xD back to T2x. The diode 2T xD is turned off and thus experiences recovery losses while T2x faces turn-on losses. This situation is depicted in Figure 3-14c. The commutations at negative phase current are illustrated in Figure 3-14e and Figure 3-14f. The distribution of the switching losses is summarized in Table 3-9.
Table 3-9 Switching losses in the three-level FLC VSC
3.3.1.1.2. Sine-Triangle Modulation The 3L-FLC VSC is modulated by a sine-triangle modulation with an addition of 1/6 of the third harmonics according to equation (3-7). The modulation of this converter can be seen in Figure 3-15a. In the FLC VSCs, there is one carrier signal per commutation cell and the commutations of one commutation cell are determined by the comparison of the carrier and the reference signals. Two carrier signals are shifted by TC/2, resulting in four commutations per phase during one period TC. In order to generate the switching signals, two triangular voltage waveforms Utri,cell,1 and Utri,cell,2 are compared with three control voltage waveforms that are 120° out of phase (which is drawn for 15fm = ). In order to trigger the switches, the following algorithm can be used. The gating signals and switching sequence according to Figure 3-12 are depicted in Figure 3-15b.
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 27
Figure 3-15 Voltage waveforms of the 3L-FLC VSC: (a) control signals and triangular signals,
(b) gating signals in phase a, (c) phase-midpoint output voltage UaM, (d) line-to-line output voltage Uab, (e) common mode voltage UnM
0 90° 180° 270° 360°
Udc / 2
-Udc / 2
0
Udc
-Udc
0
Udc
-Udc
0
Utri,cell,2 Ucon, aUcon, b Ucon, c
1
10
0
Vg1, a
Vg2, a
(a)
(b)
(c)
(d)
UaM
Uab
(e)
Utri,cell,1
Udc / 2
-Udc / 2
Udc / 2
-Udc / 2
-Udc
0
UdcUnM
28 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The output voltage waveform of the three-phase 3L-FLC VSC according to Figure 3-12 is depicted in Figure 3-15c to Figure 3-15e. The phase-to-midpoint voltages of the 3L-FLC VSC, e.g. UaM, comprise three voltage levels, viz. +Udc/2, 0, -Udc/2 (see Figure 3-15c) and the line-to-line voltages, e.g. Uab, comprise five voltage levels, viz. +Udc, +Udc/2, 0, -Udc/2, -Udc (see Figure 3-15d). The connection of two considered phases to the opposite dc rails gives rise to the maximum line-to-line voltage of ±Udc. The common mode part of the phase voltages drops between load star point "n" and converter midpoint "M". The common mode voltage depicted in Figure 3-15e is calculated according to equation (3-9). The common mode voltage can consist of the voltage levels of ±2Udc/3, ±Udc/2, ±Udc/3, ±Udc/6, and 0.
For a constant carrier frequency, the 3L-NPC VSC generates half of the switching losses than the 3L-FLC VSC, where two commutation cells switch during one period of the carrier frequency (TC = 1/fC). However, whereas the first carrier band of the line-to-line voltage of the 3L-NPC VSC occurs around the carrier frequency, the first carrier band is centred around two times the carrier frequency in the 3L-FLC VSC (f1Cb = 2fC), as shown in Figure 3-16.
Figure 3-16 Harmonic spectrum of the 3L-FLC VSC: (a) phase-neutral point output voltage,
(b) line-to-line output voltage
3.3.1.2. Four-Level Flying Capacitor Voltage Source Converter (4L-FLC VSC)
Figure 3-17 shows the structure of the three-phase 4L-FLC VSC. For this converter, the capacitors C1x and C2x are ideally charged to one-third and two-thirds of the dc voltage respectively. The four voltage levels are obtained by the relationships shown in Table 3-10. As with the three-level flying capacitor converter, the highest and lowest switching states do not change the charge of the capacitors. The two intermediate voltage levels contain redundant states so that both capacitors can be regulated to their ideal voltages.
In order to generate the switching signals, three triangular voltage waveforms ( )1 2 3tri ,cell ,iU i , ,= are compared with three control voltage waveforms that are 120° out of phase. The three carrier
1 mf 2mf 3mfHarmonic Order
10-3
10-3
100
( )aM h
dc
UU
( )ab h
dc
UU
100
1 3 mf 2mf 3mf
(a)
(b)
Har
mon
ic M
agni
tude
(p.u
.)H
arm
onic
Mag
nitu
de(p
.u.)
mf = 15, ma = 1.15
mf = 15, ma = 1.15
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 29
signals are shifted by TC/3, resulting in six commutations per phase during one period TC. The modulation of the 4L-FLC converter topology can be seen in Figure 3-18a for mf = 15.
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 31
The phase-to-midpoint voltages of the 4L-FLC VSC, e.g. uaM, comprise four voltage levels, viz. ±Udc/2 and ±Udc/6 (see Figure 3-18b) and the line-to-line voltages, e.g. Uab, comprise seven voltage levels, viz. ±Udc, ±2Udc/3, ±Udc/3, 0 (see Figure 3-18c). The common mode voltage UnM can assume the voltage levels of ±2Udc/3, ±5Udc/9, ±4Udc/9, ±Udc/3, ±2Udc/9, and ±Udc/9 (see Figure 3-18d).
The harmonic spectrum of phase voltage and line-to-line voltage are depicted in Figure 3-19. The first carrier band harmonics of the 4L-FLC VSC occurs at three times the corresponding carrier frequency (f1Cb = 3fC).
Figure 3-20 shows the transitions between two voltage levels in the 4L-FLC VSC. Some of these transitions (dashed lines) force all switches of the leg to switch. Nevertheless, these critical transitions can be used to achieve the full control of the voltages of the floating capacitors.
Figure 3-19 Harmonic spectrum of the 4L-FLC VSC: (a) phase-neutral point output voltage,
(b) line-to-line output voltage
Figure 3-20 Transitions between voltage levels for the Four-Level Flying Capacitor
off off off
off off on off on on
off on off
on off off
on off on
on on off
on on on
S3x S2x S1x S3x S2x S1x S3x S2x S1x S3x S2x S1x
6dc
xMUU = −
6dc
xMUU =
2dc
xMUU = −
2dc
xMUU =
1 mf 2mf 3mfHarmonic Order
10-3
10-3
100
( )aM h
dc
UU
( )ab h
dc
UU
100
1 3 mf 2mf 3mf
(a)
(b)
Har
mon
ic M
agni
tude
(p.u
.)H
arm
onic
Mag
nitu
de(p
.u.)
mf = 15, ma = 1.15
mf = 15, ma = 1.15
32 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
3.4. Series Connected H-Bridge Voltage Source Converter (SCHB VSC) This class of multi-level converters is based on a series connection of single-phase converters (Figure 3-21), and the earliest reference to them appeared in 1975 [128] but several recent patents have been obtained for this topology as well [129], [130], [131]. This converter topology has several advantages that have made it attractive to medium and high power drive applications [86]. Since this topology consists of series power conversion cells, the voltage and power level may be easily scaled. The dc link supply for each H-bridge converter element must be provided separately. The ability to synthesize higher number of output voltage levels with an excellent harmonic spectrum utilizing low-cost low-voltage power semiconductors and capacitors are important advantages of this topology [86]. However, drawbacks of this topology are the large number of power devices and of voltages required to supply each cell with a complex and expensive isolated transformer, as well as control the complexity [126], [129].
Figure 3-21 Three-phase configuration for the N-Level H-Bridges VSC
3.4.1.1. Circuit Configuration The circuit of Figure 3-22 shows the basic topology of an H-bridge converter used for the implementation of SCHB VSCs. It is based on the simple, four switches converter, which is usually used for single-phase applications. A three-phase diode rectifier, fed by an isolated transformer, charges the dc capacitor. The dc voltage feeds a single-phase IGBT bridge, which generates the PWM output of the power cell.
c
iph,a
n´
Udcpb
Udc2b
Udc1b
idcpb
idc2b
idc1b
b
pbn´U
2bn´U
1bn´U
Udcpc
Udc2c
Udc1c
idcpc
idc2c
idc1c
pcn´U
2cn´U
1cn´U
Udcpa
Udc2a
Udc1a
idcpa
idc2a
idc1a
a
pan´U
2an´U
1an´U
2LaT
2LaT
2RaT
2RaT
1LaT
1LaT
1RaT
1RaT
2 LbT
2 LbT
2 RbT
2 RbT
1LbT
1LbT
1RbT
1RbT
2LcT
2LcT
2RcT
2RcT
1LcT
1LcT
1RcT
1RcT
pLaT
pLaT
pRaT
pRaT
pLbT
pLbT
pRbT
pRbT
pLcT
pLcT
pRcT
pRcT
n
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 33
Figure 3-22 Typical power cell (H-bridge) converter
3.4.1.2. Switch States and Commutations Each cell consists of two half-bridge configurations. The labels TL and TR are used to identify the transistors as well as the transistor logic (1 = on and 0 = off). Since the transistors are always switched in pairs, the complement transistors are labelled LT and RT accordingly. In order to prevent a short circuit, the complementary leg switches are not switched simultaneously. In other words, whatever state the top switch is in (either on or off) the bottom switch must be in the opposite. The switch positions for the three possible states of each phase leg are given in Table 3-11.
The current paths for positive and negative phase currents iph are depicted in Figure 3-23. The zero state "0" can be generated in two ways, depending on the direction of iph. Therefore, if either top switches (TL, TR) or bottom switches ( L RT ,T ) are turned on, the output voltage will lead to zero.
In positive "+" and negative "-" states, two diagonally opposite semiconductors, (TL, RT ) or (TR,
LT ), lie within the current path, either two active switches or two diodes. Therefore, each typical H-bridge cell can only produce three distinct voltage levels.
It should be noted that each of the switches must block the dc link voltage Udc/2. The maximum switch/diode current is the maximum phase current phi . These parameters determine the basic requirements for rating the main semiconductors. The distribution of the conduction losses is summarized in Table 3-12.
Switching losses are created by the commutation processes between the different switch states. Two complement switches in each leg, (TR, RT ) or (TL, LT ), are involved in (+ → 0) and (0 → –) commutations. For a positive phase current iph > 0, the commutation (+ → 0) is initiated by the turn-off of TL in the first leg and the current is forced from TL to LD The switch RT stays turned on. Only two complement switches in the first leg are involved in this commutation.
Essential turn-off losses occur in TL. In the second leg, the commutation (+ → 0) is initiated by the turn-off of RT and the current is forced from RT to DR. The switch TL stays turned on. Only two complement switches in the second leg are involved in this commutation (TR, RT ). Essential turn-off losses occur in RT .
For the reverse commutation (0 → +), all switching transitions take place in the reverse order.
idc
L
L
T
T
R
R
T
T
L
L
D
D
R
R
D
D
an ag n gU U U′ ′= −a
g
2dcU
RS
iph
n′
34 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
For example, in the second leg, TR is turned off first, followed by the turn-on of RT after the dead time. Recovery losses occur in DR while RT experiences turn-on losses.
Table 3-11 Switch positions for the single-phase H-bridge cell
Figure 3-23 Conduction path of the single-phase H-bridge cell: (a) positive, (b, c) zero, and (d)
negative states
Table 3-12 Conduction losses in the single-phase full-bridge converter
State LS RS LS RS Uag Un´g Uan´ Positive “+” 1 0 0 1 Udc/2 0 Udc/2
State LT LD RT RD LT LD RT RD Positive phase current
“+” (Uag = Udc/2) × × × × “0” (Uag = 0) × ×
“-”(Uag = -Udc/2) × × Negative phase current
“+” (Uag = Udc/2) × × × × “0” (Uag = 0) × ×
“-”(Uag = -Udc/2) × ×
LT
LT
RT
RTLD
LD
RD
RD
a n′
LT
LT
RT
RTLD
LD
RD
RD
a n′
(a) (b)
(c) (d)
2dcU
2dcU
LT
LT
RT
RTLD
LD
RD
RD
a n′2dcU
LT
LT
RT
RTLD
LD
RD
RD
a n′2dcU
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 35
The situation for these commutations is visualized in Figure 3-24a, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled.
The commutation (0 → –) in the first leg is started by the active turn-off of the switch TL, forcing the current from its path through LD . DR has already been in the on state. TL faces turn- off losses. Again, for the reverse commutation (– → 0), all switching transitions take place in the reverse order. LT is turned off and TL turned on after a dead time.
Figure 3-24 Commutations and switching losses in the H-bridge cell: (a) and (b) for positive
load current, (c) and (d) for negative load current
36 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
After triggering TL, the phase current commutates from LD back to TL. Diode LD is turned off and thus takes over blocking voltage and experiences recovery losses. TL faces turn-on losses. In the second leg, the commutation (0 → –) is started by the active turn-off of the switch RT , forcing the current from its path through DR. LD has already been in the on state. RT faces turn-off losses. Again, for the reverse commutation (– → 0), all switching transitions take place in the reverse order. TR is turned off and RT turned on after a dead time. After triggering RT , the phase current commutates from DR back to RT . Diode DR is turned off and thus takes over blocking voltage and experiences recovery losses. RT faces turn-on losses. These situations are depicted in Figure 3-24b. The commutations at the negative phase current are illustrated in Figure 3-24c and Figure 3-24d. The distribution of the switching losses is summarized in Table 3-13.
Table 3-13 Switching losses in the single-phase full-bridge converter
3.4.1.3. Sine-Triangle Modulation Each cell is modulated by a sine-triangle modulation with an addition of 1/6 of the third harmonic, as shown in Figure 3-25a. There are two carrier signals 1 2 , tri triU U and the commutations of one commutation cell (half bridge) are determined by the comparison of the corresponding carrier signal and the reference signal Ucon. The two carrier signals are shifted by TC/2 (180° phase difference with respect to each other). Thus, there are four commutations during one period of the carrier signal. As shown in Figure 3-25a, the comparison of Ucon with
1triU results in the following logic signals to control the switches in the first leg
( )( )
1
1
: : :2
0 : : :
dccon tri L L
ag
con tri L L
U if U > U T on,T offU
if U < U T off ,T on
⎧⎪= ⎨⎪⎩
(3-27)
For controlling the second leg switches, 2triU is compared with the same control signal, which yields the following
( )
( )2
2
0 : : :
: : :2
con tri R R
n g dccon tri R R
if U > U T off ,T onU U if U < U T on,T off
′
⎧⎪= ⎨⎪⎩
(3-28)
State LxT LxD RxT RxD LxT LxD RxT RxD Positive phase current
× × 0+ ↔ × × × × 0 ↔ − × ×
Negative phase current × × 0+ ↔ × × × × 0 ↔ − × ×
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 37
Figure 3-25 Voltage waveforms of the H-bridge cell: (a) control signals Ucon and triangular
signals Utri,1 and Utri,2, (b) a-leg output voltage Uag, (c) n´-leg output voltage Un´g, (d) load voltage Uan´
Because of the diodes in anti-parallel with the switches, the foregoing voltage given by equations (3-31) and (3-32) are independent of the direction of the output current iph.
The output voltages of leg a and leg n´ with respect to the negative dc rail g are shown in Figure 3-25b and Figure 3-25c respectively.
The H-bridge output voltage waveform Uan´ according to Figure 3-22 is depicted in Figure 3-25d. This voltage comprises three voltage levels, viz. ±Udc/2 and 0.
Because two legs of the H-bridge are controlled separately, as mentioned in the previous section, the first carrier band harmonics of the output voltage occur at twice the corresponding carrier
0
-Udc
Udc
0
0
0
0 90° 180° 270° 360°
Utri,1 UconUtri,2
Uag
Un´g
Uan´
(a)
(b)
(c)
(d)Uan´,1
2dcU
2dcU
2dcU
2dcU
−
38 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
frequency (f1Cb = 2fC). This advantage appears in the harmonic spectrum of the output voltage waveform, as shown in Figure 3-26. If we choose the frequency modulation ratio mf to be even, the output voltage waveforms of any one of the legs Uag and Un´g are displaced by 180° of the fundamental frequency, with respect to each other. Therefore, the harmonic components at the switching frequency in any one of the legs have the same phase, since the output voltage waveforms are 180° displaced and mf is assumed to be even [4]. This results in the cancellation of the harmonic component at the sidebands of the switching frequency in the output voltage.
Moreover, the use of this PWM voltage switching causes a smaller ripple on the dc current side. We notice that when both the upper switches are on, the output voltage is zero. The output current circulates in a loop through (TL, DR) or (DL, TR), depending on the direction of iph. During this interval, the current idc is zero. A similar condition occurs when both bottom switches LT and RT are turned on.
Figure 3-26 Harmonic spectrum of the H-bridge output voltage
3.4.2.1. Circuit Configuration Converters having additional phases can be realized by simply adding multiple numbers of H-bridge converter legs (Figure 3-22). A simplified diagram of a three-phase two-level H-bridge converter is shown in Figure 3-27. It contains 12 unidirectional active switches with inverse diodes.
Figure 3-27 Three-phase configuration for the 2L-H-Bridges Voltage Source Converter
c
iph,a
a
Udc,c
LcS
LcS
RcS
RcS
idc,c cn´U
Udc,a
LaS
LaS
RaS
RaS
idc,a an´U
Udc,b
LbS
LbS
RbS
RbS
idc,b bn´Ub
n´
abU bcU
n
1 3 mf 2mf 3mf
( )ab h
dc
UU 2
100
10-3
Harmonic Order
Har
mon
ic M
agni
tude
(p.u
.)
mf = 15, ma = 1.15
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 39
3.4.2.2. Switch States and Commutations In order to produce three levels in each phase leg, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time. The labels SLx and SRx are used to identify the transistors in each phase (x = a, b, c). Since the transistors are always switched in pairs, the complement transistors are labelled LxS and RxS accordingly. The switch positions for three possible states of each phase leg remain the same as for a single-phase H-bridge (see Table 3-11). The distribution of the conduction and switching losses are the same as for a single-phase H-bridge (see Table 3-12 and Table 3-13).
3.4.2.3. Sine-Triangle Modulation
The fundamental modulation concept remains the same as for a single-phase H-bridge. The modulation method for a three-phase 2L-H-Bridge is shown in Figure 3-28a. It demonstrates that the difference between the three-phase 2L-H-Bridge and a single-phase H-bridge are the two-phase legs which were added to the first. Furthermore, the reference signals for each phase leg are now displaced by 120°. Therefore, each phase leg is controlled separately by comparing a reference signal ,con xU (x=a, b, c) with the triangular waveforms 1 2 , tri triU U .
The commutations are determined by the comparison of the corresponding carrier signal and the reference signal. The two carrier signals are shifted by TC/2. Thus, there are four commutations per phase during one period of the carrier signal.
In order to generate the gate signals, the same algorithm as for a single-phase H-bridge can be used
( ) ( )
( ) ( )
1 2
1 2
: : : :2
: : : :2
dccon,x tri Lx Lx con,x tri Rx Rx xn
dccon,x tri Lx Lx con,x tri Rx Rx xn
UU > U T on,T off ,U > U T off ,T on U
UU < U T off ,T on ,U < U T on,T off U
else
′
′
⇒ =
⇒ = −
0xn U ′
⎧⎪⎪⎪⎨⎪
⇒ =⎪⎪⎩
(3-29)
Because of the inverse diodes in anti-parallel to the switches, the voltage given by equation (3-29) is independent of the direction of the output current iph.
The output voltage waveforms of the three-phase 2L-H-Bridge according to Figure 3-27 are depicted in Figure 3-28. The phase voltages (e.g. Uan´) comprise three voltage levels, viz. ±Udc/2 and 0 [see Figure 3-28c], and the line-to-line voltages (e.g. Uab) comprise five voltage levels, viz. ±Udc, ±Udc/2, and 0 (see Figure 3-28d).
The harmonic spectrum of the phase voltage and the line-to-line voltage are illustrated in Figure 3-29a and Figure 3-29b respectively (which is drawn for 15fm = ). Like in a single-phase H-bridge, the first carrier band harmonics of the 2L-H-Bridge occurs at twice the corresponding switching frequency (f1Cb = 2fC).
40 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-28 Voltage waveforms of the three-phase 2L-H-Bridge cell: (a) control signals Ucon,x
and triangular signals Utri,1 and Utri,2, (b) gate signals, (c) output phase voltage, (d) output line-to-line voltage
0 90° 180° 270° 360°
0
Udc
-Udc
0
Udc
-Udc
0
Utri,2 Ucon, a Ucon, b Ucon, c
1
10
0
VgL, a
VgR, a
(a)
(b)
(c)
(d)
Uan´,1
Uab
Utri,1
Uan´
2dcU
2dcU
−
2dcU
2dcU
−
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 41
Figure 3-29 Harmonic spectrum of the three-phase 2L-H-Bridge cell: (a) phase output voltage,
(b) line-to-line output voltage
3.4.3. Introduction to the Series Connected Two-Level H-Bridge Voltage Source Converter (SC2LHB VSC)
In traditional converter topologies such as the 2L-VSC or 3L-NPC VSC, the device with the maximum available voltages (e.g. 6.5kV IGBT) is connected in series to reach the required line-to-line output voltage (Ull > 3.3kV and Ull > 4.16kV). The concept of the generalized Series Connected Two-Level H-Bridge Voltage Source Converter (SC2LHB VSC) is shown in Figure 3-30. It is based on series connected isolated H-bridge cells rather than series connected devices. The patent for the series connected isolated H-bridge cell was originally obtained by Robicon [129]. The SC2LHB VSC is a popular power converter for motor drives [42], [46], [129], [130], power supplies [49], [132], and ac power systems [52], [54], [57], [58].
The SC2LHB VSCs will be designated according to the voltage levels of the individual H-bridge cells. The step of the output voltage is comparatively small and equal to the dc bus voltage of one H-bridge cell (order of 600 volts for a 460-volt input). To attain the rated medium output voltage, all single-phase low-voltage H-bridge cells are connected in series, only using low-cost low-voltage devices (e.g. 1.7kV IGBT).
The total virtual dc link voltage Udc,tv differs according to the necessary line-to-line output voltage of the converter. This voltage depends on the number of series connected H-bridges p and is determined by
2dc,tv dc ,HBU p U= × × (3-30)
Using the same dc link voltage Udc,HB for each H-bridge cell, the converter synthesizes an output phase voltage (e.g. Uan´, Ubn´ , Ucn´)
1 2xn xn xn pxnU U U ... U′ ′ ′ ′= + + + (3-31)
Har
mon
ic M
agni
tude
(p.u
.)H
arm
onic
Mag
nitu
de(p
.u.)
mf = 15, ma = 1.15
mf = 15, ma = 1.15( )an´ h
dc
UU 2
( )ab h
dc
UU 2
1 3 mf 2mf 3mf
10-3
10-3
100
100
1 mf 2mf 3mfHarmonic Order
(a)
(b)
42 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-30 Series Connected Two-Level H-Bridge Voltage Source Converter with p series H-
bridge cells per phase
with a number of output phase voltage levels
N=2p+1 (3-32)
and a number of output line-to-line voltage levels 2 1llN N= − (3-33)
The number of series H-bridge cells is chosen typically from 2 to 5, for the worldwide standard machine voltages of 2.3 to 7.2kV. With two power cells per phase (p = 2), the circuit of Figure 3-30 can produce five distinct phase voltage levels (N = 5). With three, four, and five cells per phase; 7, 9, and 11 distinct phase voltage levels are available. “There are several families of H-bridge cells with the same input voltage (460, 630, and 690) that are capable to produce (800,
a
b
c
0
3 ∼
1α
3
1α
3
1α
3
1 1 La RaS S
1 1 La RaS S
1 1 Lb RbS S
1 1 Lb RbS S
1 1 Lc RcS S
1 1 Lc RcS S
2α
3
2α
3
2α
3
2 2 La RaS S
2 2 La RaS S
2 2 Lb RbS S
2 2 Lb RbS S
2 2 Lc RcS S
2 2 Lc RcS S
pα
3
pα
3
pα
3
pLa pRaS S
pLa pRaS S
pLb pRbS S
pLb pRbS S
pLc pRcS S
pLc pRcS S
n
nph ,ai
pan´U
pbn´U
pcn´U
2an´U
1an´U
2bn´U
1bn´U
2cn´U
1cn´U
abU
anU
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 43
1100, and 1200) line-to-line output voltages (per cell) for rated currents ranging from 70 to 1000 amperes [35].”
For the modulation, two triangular carrier signals are needed for each cell, which is the same as in the single-phase H-bridge. It should be noted that the pair of triangular carrier signals applied in each cell have a phase shift of 180°/p, in contrast to the triangular carrier of the previous H-bridge cell, with the first H-bridge cell as reference cell. With this modulation, the frequency of the first harmonics carrier band of the output voltage is equal to
1Cb Cf =2 p f× × (3-34)
where fC denotes the carrier frequency.
Due to many different output voltage levels and the high frequency f1Cb, the output voltage and current harmonics are low; and therefore, the filtering processes are easier. Each additional level is another "degree of freedom" in reducing the output harmonics.
It is possible to add an extra tier of H-bridge cells that enables the drive to operate with an increased output voltage (p+1)/p capability. Since the output voltage is distributed uniformly between the H-bridge cells, there is some redundancy which allows the drive to operate with one shortened H-bridge. If an H-bridge fails, its output is shortened by the controller without any user intervention. The drive remains at work and operates with nominal output voltage.
The maximum input and output voltages of each H-bridge cell are equal to the instantaneous dc link voltage, according to Figure 3-22. Therefore, the dc link capacitor acts as a large snubber for all the devices.
All H-bridge cells carry the same current at the output fundamental voltage. This results in an equal power among all H-bridge cells, a simple control structure, and modularity of the control.
Although the H-bridge could be constructed with a variety of low voltage semiconductor devices, the LV-IGBT is an excellent choice due to its extremely low gate power and fast switching behaviour. Robicon utilizes low-cost low-voltage IGBTs, e.g. 1700V, for its medium voltage drives [36]. The drive can produce 2.3kV, 3.3kV, 4.16kV, and 6kV line-to-line voltages with two, three, four, and five H-bridge cells in series per phase.
Other important advantages of this drive are a minimal common mode voltage and a potentially low dv/dt in the output voltages.
However, the dc link supply for each H-bridge cell must be provided separately. This is accomplished by multiple isolated secondary windings of an integral isolation transformer. The transformer is more complex and expensive than customary, but it performs several very important functions. First, it ensures that any common mode voltage does not have to be supported by the motor insulation. Second, by the phase shift
3606p= p
α°
(3-35)
between the secondary windings, it is possible to cancel most of the harmonic currents drawn by the individual power cells so that the primary currents are nearly sinusoidal (the pulse number at the primary is equal to 6p). The transformer impedance is consciously made larger than normal to limit the inrush current and to reduce the harmonics. Due to the excellent harmonic performance of the grid side, the reduced input filter compensates the extra cost of the transformer. The transformer efficiency is typically 98.5%. Table 3-14 summarizes the quantities comparison for this topology with different H-bridge cells per phase.
44 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Table 3-14 Quantities comparison of the SC2LHB VSC
3.4.3.1. Series Connected Two-Level H-Bridge Voltage Source Converter with Two Power Cells per Phase Leg (5L-SC2LHB VSC)
3.4.3.1.1. Circuit Configuration
Figure 3-31 shows the 5L-SC2LHB VSC utilizing two three-level H-bridge cells in series per phase. This structure may be related to Figure 3-30 regarding the points labelled a and n´. It contains 24 unidirectional active switches with inverse diodes, 6 separated dc link capacitors, and a 12-pulse transformer with two secondary windings which are shifted 30° with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of Udc,HB, the resulting converter can operate with five output phase voltage levels (e.g. Uxn´).
Figure 3-31 5L-SC2LHB Voltage Source Converter
3.4.3.1.2. Switch States and Commutations In order to produce five levels, the switches are controlled so that only two of the four switches in each H-bridge cell are turned on at any time. The labels SpLx and SpRx are used to identify the switches as well as the switches logic (1 = on and 0 = off, p = 1, 2). Since the
a
0
3 ∼
0
3
0
3
0
3
1 1 La RaS S
1 1 La RaS S
1 1 Lb RbS S
1 1 Lb RbS S
1 1 Lc RcS S
1 1 Lc RcS S
30
3
30
3
30
3
2 2 La RaS S
2 2 La RaS S
2 2 Lb RbS S
2 2 Lb RbS S
2 2 Lc RcS S
2 2 Lc RcS S
n
2anU
1anU
2bnU
1bnU
2cn´U
1cnU
b
c
Number of series connected H-Bridges p 2 3 4 5 p Number of phase output voltage level N 5 7 9 11 2p+1 Number of line-to-line output voltage level Nll 9 13 17 21 4p+1 Number of dc-link capacitors 6 9 12 15 3p Transformer phase displacement αp 30° 20° 15° 12° 60/p Number of the carrier signals 4 6 8 10 2p Carrier phase shift displacement 90° 60° 45° 36° 180/p
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 45
switches are always switched in pairs, the complement switches are labelled pLxS and pRxS accordingly. In order to prevent a short circuit, the complementary leg switches are not switched simultaneously. In other words, in whatever state that the top switch is, the bottom switch must be in the opposite. The switch positions for five possible states of each phase leg as well as the individual H-bridge voltage are given in Table 3-15. It shows that there are six and four redundant possibilities for switching Uxn´ = 0 and Uxn´ = ±Udc,HB.
Figure 3-32 illustrates the transitions between the output voltage steps. The number of commutations between each two adjacent voltage levels are marked in grey. These critical transitions can be used to achieve the full control of the voltages. As can be seen from this Figure, some of these transitions force three switches to switch.
For the following discussion of commutations, only one of the transition states is assumed, as indicated in bold line in Figure 3-32.
The current paths for positive and negative phase currents iph are depicted in Figure 3-33. If either the diagonally opposite semiconductors ( )1 1 2 2Lx Rx Lx RxS ,S ,S ,S or ( )1 1 2 2Lx Rx Lx RxS ,S ,S ,S are turned on, i.e. either two active switches or two diodes, then the phase-to-ground output voltage will lead to 2Udc,HB or -2Udc,HB (Table 3-15).
The positive and the negative states Udc,HB and –Udc,HB can be generated, if either for example, the switches ( )1 1 2 2Lx Rx Lx RxS ,S ,S ,S or ( )1 1 2 2Lx Rx Lx RxS ,S ,S ,S are turned on (Table 3-15).
The zero state can be generated if the upper switches ( )1 1 2 2Lx Rx Lx RxS ,S ,S ,S in both H-bridges lie within the current path. Therefore, each phase-to-ground can produce five distinct voltage levels. It should be noted that each of the switches must block the dc link voltage Udc,HB (e.g. Udc/4), compared to Udc/2 in the 3L-NPC and 3L-FLC converters, to achieve the same output voltage.
The distribution of the conduction and switching losses are the same as for a single-phase H-bridge converter (refer to section 3.4.1.2).
46 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-32 Transitions between voltage levels for the 5L-SC2LHB VSC
3.4.3.1.3. Sine-Triangle Modulation There are different PWM methods which have been extended for the use in an H-bridge converter by applying multiple carriers. These methods are described in many publications in the technical literature [28], [43], [50], [55], [59], [60], [61]. They can be categorized into three groups: Phase Shifted (PS), Carrier Disposition (CD), and Hybrid (H) method. These methods are described in Appendix in detail. The following subsection only discusses the PS method due to its balanced switch utilization and simple implementation.
This PWM method uses four carrier signals of the same amplitude and frequency, which are phase shifted by TC/4 with respect to each other, where TC is the period of the carrier signal. The modulation method for the 5L-SC2LHB VSC is shown in Figure 3-34a.
The triangular carriers Utri,L1, Utri,R1 for the first H-bridge cell and the triangular carriers Utri,L2, Utri,R2 for the second H-bridge cell are considered (one carrier signal for each column). The commutations are determined by the comparison of the corresponding carrier signal and the reference signal Ucon,x (x = a, b, c). There are eight commutations per phase during one period of carrier signal TC. The gate signals can be produced by the following algorithm
( ) ( )( ) ( )
, , , ,
, , , ,
> : , : or < : , :
> : , : or < : , :
1, 2
con x tri Lp pLx pLx con x tri Lp pLx pLx
con x tri Rp pRx pRx con x tri Rp pRx pRx
U U S on S off U U S off S on
U U S on S off U U S off S on
p
⎧⎪⎪⎨⎪ =⎪⎩
(3-36)
131133
311133
133311
313311
311331
131331
113113
133113
2xn dc,HBU U=
State
67891011
2
67891011
3
67891011
4
67891011
5
12
13
14
15
16
2xn dc,HBU U= −
xn dc ,HBU U= −xn dc,HBU U=0xnU =
1
State
State
State
State1
1
1
1
1
1
1
1
Number of the commutations between states
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 47
Figure 3-33 Conduction path of the 5L-SC2LHB VSC (according to Figure 3-32)
2 2 Lx RxS S
2 2 Lx RxS S
1 1 Lx RxS S
1 1 Lx RxS S
State 4
2 2 Lx RxS S
2 2 Lx RxS S
1 1 Lx RxS S
1 1 Lx RxS S
State 14
dc ,HBU
dc,HBU
2 2 Lx RxS S
2 2 Lx RxS S
1 1 Lx RxS S
1 1 Lx RxS S
State 16
dc,HBU
dc,HBU
2 2 Lx RxS S
2 2 Lx RxS S
1 1 Lx RxS S
1 1 Lx RxS S
State 1
4dc ,HB dcU U /=
4dc ,HB dcU U /=
dc ,HBU
dc,HBU
2 2 Lx RxS S
2 2 Lx RxS S
1 1 Lx RxS S
1 1 Lx RxS S
State 7
dc,HBU
dc,HBU
48 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The resulting gate signals for the 5L-SC2LHB VSC are shown in Figure 3-34b, which directly yields the switch states of 1LxS , 1RxS , 2LxS and 2RxS . The output voltage waveforms of the 5L-SC2LHB VSC according to Figure 3-31 are depicted in Figure 3-34c to Figure 3-34e. The converter ground n´ is isolated from the load neutral point n and each phase voltage Uan´, Ubn´, and Ucn´ is directly controlled by the ac output of the individual multi-level H-bridge cells. Due to the same dc voltage value of each cell (i.e. Udc,HB = Udc/4), the phase output voltage of the 5L-SC2LHB converter, e.g.
( )
( )
, , 1 , , 1 , , 2 , , 2
, , 1 , , 1 , , 2 , , 2
, , 1
> , > , > , > 2
> , < , > , > 4
0 > ,
dccon x tri L con x tri R con x tri L con x tri R
dccon x tri L con x tri R con x tri L con x tri R
con x tri Lxn
U if U U U U U U U U
U if U U U U U U U U
if U U UU ′ = ( )
( ), , 1 , , 2 , , 2
, , 1 , , 1 , , 2 , , 2
, , 1 , , 1 , , 2 ,
< , > , <
> , < , < , < 4
< , < , < , <2
con x tri R con x tri L con x tri R
dccon x tri L con x tri R con x tri L con x tri R
dccon x tri L con x tri R con x tri L con x
U U U U U
U if U U U U U U U U
U if U U U U U U U
−
− ( ), 2 tri RU
⎧⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎩
(3-37)
comprises five voltage levels, viz. ±Udc/2, ±Udc/4, and 0 (see Figure 3-34c).
The line-to-line output voltages of the 5L-SC2LHB converter, e.g
ab an bn´U U U = − (3-38)
comprise nine voltage levels, viz. ±Udc, ±3Udc/4, ±Udc/2, ±Udc/4, and 0 (see Figure 3-34d).
The load phase voltages Uan, Ubn, and Ucn, as depicted in Figure 3-34e, may be expressed in terms of the phase voltages by [11]
The load phase voltages comprise thirteen voltage levels, viz. ±7Udc/12, ±Udc/2, ±5Udc/12, ±Udc/3, ±Udc/4, ±Udc/6, and 0.
Table 3-16 summarizes the output voltages and their corresponding voltage levels.
The spectrum of the phase voltage and line-to-line output voltage waveforms are depicted in Figure 3-35a and Figure 3-35b respectively (at 1 15am .= and 15fm = ). As can be seen in these Figures, the first carrier band of the output voltages is centred around four times the carrier frequency (f1Cb = 4fC) (equation 3-33). Hence, an output filter of the 5L-SC2LHB VSC would be smaller than the corresponding filters of conventional converters such as the 3L-NPC VSC [25].
Table 3-16 The output voltage levels of the 5L-SC2LHB VSC
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 49
Figure 3-34 Voltage waveforms of the 5L-SC2LHB VSC: (a) control signals Ucon,x and
triangular signals Utri,L1, Utri,L2, Utri,R1 and Utri,R2, (b) gate signals, (c) output phase-to-ground voltage Uan´, (d) output line-to-line voltage Uab, (e) output load-phase voltage Uan
, 2g RV
Ucon, a
(a)
Uan´
1
01
01
01
0
Udc / 4
0
-Udc / 4
0 90° 180° 270° 360°
Udc /2
Udc
-Udc
0
-Udc /2
Udc / 2
Udc
-Udc
0
-Udc / 2
Utri,L2 Utri,R2 Utri,L1 Utri,R1
(b)
(c)
(d)Uab
, 2g LV
, 1g LV
, 1g RV
Uan´,1
(e)Uan
Udc / 2
-Udc / 2
3Udc/5
0
2Udc/5Udc/5
-Udc/5-2Udc/5-3Udc/5
50 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-35 Harmonic spectrum of the 5L-SC2LHB VSC
3.4.3.2. Series Connected Two-Level H-Bridge Voltage Source Converter with Three Power Cells per Phase Leg (7L-SC2LHB VSC)
3.4.3.2.1. Circuit Configuration
The structure of the 7L-SC2LHB VSC utilizing three H-bridge cells in series per phase leg is similar to Figure 3-30, but with p = 3. It contains 36 unidirectional active switches with inverse diodes and 9 separated dc link capacitors as well as an 18-pulse transformer with three secondary windings which are shifted 20° with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of Udc,HB, the resulting converter can operate with seven output voltage levels (e.g. Uxn´) by using the combinations of the three H-bridge converter voltages.
3.4.3.2.2. Switch States and Commutations The fundamental concepts for the 7L-SC2LHB VSC remain the same as for the 5L-SC2LHB VSC. The total number of switch states, which includes all redundancies, calculates to
2 62 2 64pswn = = = (3-40)
with p being the number of H-bridge cells per phase.
The phase output voltages (e.g. Uxn´) ±2Udc,HB (±Udc/3 according to equation (3-30)), ±Udc,HB (±Udc/6), and 0 can be generated with more than one combination, as given in Table 3-17. It shows that there are different redundant possibilities to achieve the same output voltages.
For a positive phase current, if either all diagonally opposite switches ( )1 2 3pLx pRxS ,S : p , ,= or
( )1 2 3pLx pRxS ,S : p , ,= are turned on, then the phase output voltage will lead to +3Udc,HB =
(a)
(b)
1 3 mf 2mf 3mf 4mf
1 mf 2mf 3mf 4mfHarmonic Order
( )ab h
dc
UU
( )an´ h
dc
UU
10-2
10-3
10-1
100
10-2
10-3
10-1
100
mf = 15, ma = 1.15
mf = 15, ma = 1.15
Har
mon
ic M
agni
tude
(p.u
.)H
arm
onic
Mag
nitu
de(p
.u.)
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 51
+Udc/2 or -3Udc,HB = +Udc/2. The positive and negative states +2Udc,HB and –2Udc,HB can be generated, if either only one pair of switches ( )1 2 3pLx pRxS ,S :p or or = or
( )1 2 3pLx pRxS ,S :p or or = is turned off. In order to produce the positive state +Udc,HB and the negative state –Udc,HB, only one out of three diagonally arranged switches must be turned on. The zero state can be created if all upper or lower switches in the three H-bridges lie within the current path. Therefore, each phase can produce seven distinct voltage levels, viz. ±Udc/2, ±Udc/3, ±Udc/6, and 0 (Table 3-17).
There are some redundancies to produce the output voltage levels +Udc/3, +Udc/6, and 0. Although the same output voltages are generated, the output current iph flows in different paths. This means that a different current flows in different dc link capacitors. Consequently, the dc link capacitors have different voltage profiles. The redundancies can be used to adjust the individual capacitor voltages and to balance these voltages.
To achieve minimal operating losses and power balancing, the most suitable redundancy should be selected. Regarding the optimization concern, the selected operation modes used to generate the positive and zero output voltages for a 7L-SC2LHB VSC.
Figure 3-36 Pulse width modulation for the 7L-SC2LHB VSC: (a) control signals Ucon,a and
Table 3-17 Number of redundancies in each phase voltage level of the 7L-SC2LHB VSC
Phase output voltage level Udc/2 Udc/3 Udc/6 0 -Udc/6 -Udc/3 -Udc/2 Number of redundancies at level 1 6 15 20 15 6 1
0 90° 180° 270° 360°
Udc
-Udc
0
Utri,L1
Utri,R1
Utri,L2
Utri,R2
Utri,L3
Utri,R3
Ucon,a
, 3 g LV
, 2 g LV
, 1 g LV
, 2 g RV
, 3 g RV
, 1 g RV
(a)
(b)1
01
01
01
01
01
0
52 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The redundancy combination used to produce the output voltages of +3Udc,HB, +2Udc,HB, +Udc,HB, and 0 are one, three, three, and one respectively (Table 3-17). This also applies to negative output voltages. Therefore, the total number of switch states for the 7L-SC2LHB VSC is 15, which breaks down to seven for the positive voltage, seven for the negative voltage, and one for the zero voltage.
It should be noted that each switch of the H-bridge cells must block the dc link voltage Udc/6, compared to the Udc/4 in the 5L-SC2LHB VSC, to achieve the same output voltage.
Switching losses are caused by the commutation processes between the different switch states. Only the two complement switches in each H-bridge cell are involved in the commutations.
3.4.3.2.3. Sine-Triangle Modulation The fundamental concept is the same as the 5L-SC2LHB converter. The PS modulation method uses six carrier signals of the same amplitude and frequency, which are phase shifted by TC/6 with respect to each other, where TC is the period of the carrier signal.
The modulation method for the 7L-SC2LHB VSC is shown in Figure 3-36a. Triangular carriers ( ), 1 , 1,tri L tri RU U , ( ), 2 , 2,tri L tri RU U , and ( ), 3 , 3,tri L tri RU U are considered for the first, second, and third H-bridge cell respectively (one carrier signal for each leg).
The commutations are determined by the comparison of the corresponding carrier signal and the reference signal ( ) , , ,con xU x a b c= . There are twelve commutations per phase during one period of the carrier signal TC. Gate signals can be produced by
( ) ( )( ) ( )
1 2 3
con,x tri ,Lp pLx pLx con,x tri ,Lp pLx pLx
con,x tri ,Ri pRx pRx con,x tri ,Rp pRx pRx
U > U S : on , S : off or U < U S : off , S : on
U > U S : on , S : off or U < U S : off , S : on
p , ,
⎧⎪⎪⎨⎪ =⎪⎩
(3-41)
The resulting gate signals for the 7L-SC2LHB VSC are shown in Figure 3-36b, which directly yield the switch states of 1LxS , 1RxS , 2LxS , 2RxS , 3LxS and 3RxS respectively.
( )( )
, , 1 , 2 , 3 , 1 , 2 , 3
, , 1 , 2 , 3 , 1 , 2 , , 3
, , 1 , 2
2 > , , , , ,
3 > , , , , , <
6 > , ,
dc con x tri L tri L tri L tri R tri R tri R
dc con x tri L tri L tri L tri R tri R con x tri R
dc con x tri L tri L
xn
U if U U U U U U U
U if U U U U U U U U
U if U U U
U ′
⎡ ⎤⎣ ⎦
⎡ ⎤⎣ ⎦
=
( )( )
, 3 , 1 , , 2 , 3
, , 1 , 2 , 3 , , 1 , 2 , 3
, , 1 , 2 , 3 , 1
, , < ,
0 > , , , < , ,
6 < , , , ,
tri L tri R con x tri R tri R
con x tri L tri L tri L con x tri R tri R tri R
dc con x tri L tri L tri L tri R co
U U U U U
if U U U U U U U U
U if U U U U U U
⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
⎡ ⎤− ⎣ ⎦( )( )( )
, , 2 , 3
, , 1 , 2 , 3 , 1 , 2 , , 3
, , 1 , 2 , 3 , 1 , 2 , 3
> ,
3 < , , , , , >
2 < , , , , ,
n x tri R tri R
dc con x tri L tri L tri L tri R tri R con x tri R
dc con x tri L tri L tri L tri R tri R tri R
U U
U if U U U U U U U U
U if U U U U U U U
⎧⎪⎪⎪⎪⎪⎪⎨⎪
⎡ ⎤⎪ ⎣ ⎦⎪⎪ ⎡ ⎤− ⎣ ⎦⎪⎪ ⎡ ⎤− ⎣ ⎦⎩
(3-42)
The output voltage waveform of the 7L-SC2LHB VSC is depicted in Figure 3-37. Similar to the 5L-SC2LHB VSC, the converter ground n´ is isolated from the load neutral point n and each phase-to-ground voltage Uan´, Ubn´, and Ucn´ is directly controlled by the ac output of the individual multi-level H-bridge cells. Considering the same dc voltage value Udc,HB = Udc/6 for each cell (according to equation 3-30), the phase output voltage of the 7L-SC2LHB VSC
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 53
comprises seven voltage levels, viz. ±Udc/2, ±Udc/3, ±Udc/6, and 0 (see Figure 3-37b and Table 3-18).
The line-to-line output voltages of the 7L-SC2LHB VSC comprise thirteen voltage levels, viz. ±Udc, ±5Udc/6, ±2Udc/3, ±Udc/2 ±Udc/3, ±Udc/6, and 0 (see Figure 3-37c and Table 3-18). The load phase voltage Uan is depicted in Figure 3-37d. It comprises 25 voltage levels, viz. ±2Udc/3, ±11Udc/18, ±5Udc/9, ±Udc/2, ±4Udc/9, ±7Udc/18, ±Udc/3, ±5Udc/18, ±2Udc/9, ±Udc/6, ±Udc/9, ±Udc/18, and 0 (Table 3-18).
Figure 3-37 Voltage waveforms of the 7L-SC2LHB VSC: (a) reference and triangular signals,
(b) output phase voltage Uan´, (c) output line-to-line voltage Uab, (d) output load-phase voltage Uan (mf = 15)
(a)
0 90° 180° 270° 360°
(b)
(c)
(d)
Udc/2
0
Udc/4
-Udc/2
-Udc/4
Udc
0
Udc/2
-Udc
-Udc/2
Uan´
Uan´,1
Uab
Uan3Udc/5
0
2Udc/5Udc/5
-Udc/5-2Udc/5-3Udc/5
Udc
0
Udc/2
-Udc
-Udc/2
54 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Table 3-18 The output voltages and their corresponding levels of the 7L-SC2LHB VSC
The spectrum of the phase-to-ground and the line-to-line output voltage waveforms are depicted in Figure 3-38a and Figure 3-38b respectively (at ma =1.15 and mf = 15). It becomes apparent that the first carrier band of the output voltages is centred around six times the carrier frequency (f1Cb = 6fC), according to equation 3-33.
Figure 3-38 Harmonic spectrum of the phase voltage (a) and line-to-line voltage (b) of the 7L-SC2LHB VSC
3.4.3.3. Series Connected Two-Level H-Bridge Voltage Source Converter with four Power Cells per Phase Leg (9L-SC2LHB VSC)
Figure 3-39 represents the structure of the 9L-SC2LHB VSC utilizing four H-bridge cells in
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 55
series per phase leg p = 4. It contains 48 unidirectional active switches with inverse diodes, 12 separated dc link capacitors as well as a 24-pulse transformer with three secondary windings which are shifted 15° with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of Udc,HB, the resulting converter can operate with nine voltage levels by using the combinations of the four H-bridge converter voltages.
Figure 3-39 The 9L-SC2LHB Voltage Source Converter
0
3 ∼
1α
3
1α
3
1α
3
1 1 La RaS S
1 1 La RaS S
1 1 Lb RbS S
1 1 Lb RbS S
1 1 Lc RcS S
1 1 Lc RcS S
n′
1anU ′
1bnU ′
1cnU ′
a
b
c
4α
3
4α
3
4α
3
4 4La RaS S
4 4La RaS S
4 4Lb RbS S
4 4Lb RbS S
4 4Lc RcS S
4 4Lc RcS S
nph ,ai
4anU ′
4bnU ′
4cnU ′
abU
anU
2α
3
2α
3
2α
3
2 2 La RaS S
2 2 La RaS S
2 2 Lb RbS S
2 2 Lb RbS S
2 2 Lc RcS S
2 2 Lc RcS S
2anU ′
2bnU ′
2cnU ′
3α
3
3α
3
3α
3
3 3La RaS S
3 3La RaS S
3 3Lb RbS S
3 3Lb RbS S
3 3Lc RcS S
2 2 Lc RcS S
3anU ′
3bnU ′
3cnU ′
id21a
56 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The fundamental concepts of commutations are the same as for the 7L-SC2LHB VSC. There are different redundant possibilities to generate the phase output voltage, (e.g. Uxn´), ±3Udc,HB, ±2Udc,HB, ±Udc,HB, and 0. The redundancies can be used to adjust the individual capacitor voltages and to balance cell power. Considering the optimal redundancies, the total number of switch states can be calculated by
1 52 1 2 1 31p+ − = − = (3-43)
In order to generate the gate signals, the PS modulation method is used. The commutations are determined by the comparison of the eight carrier signals, one carrier signal for each leg, and the reference signal ( ) , , ,con xU x a b c= . The carrier signals are phase shifted by TC/8 with respect to each other. The modulation method for the 9L-SC2LHB VSC is shown in Figure 3-40a. There are sixteen commutations per phase (four commutations per cell) during one period of carrier signal TC.
The gate signals can be produced by
( ) ( )( ) ( )
1 2 3 4
con,x tri ,Lp pLx pLx con,x tri ,Lp pLx pLx
con,x tri ,Ri pRx pRx con,x tri ,Rp pRx pRx
U > U S : on , S : off or U < U S : off , S : on
U > U S : on , S : off or U < U S : off , S : on
p , , ,
⎧⎪⎪⎨⎪ =⎪⎩
(3-44)
The resulting gate signals for the 9L-SC2LHB VSC are depicted in Figure 3-40b, which directly yield the switch states of 1LxS , 1RxS , 2LxS , 2RxS , 3LxS , 3RxS , 4LxS and 4RxS respectively.
The output voltage waveform of the 9L-SC2LHB VSC is illustrated in Figure 3-41. Each phase voltage Uan´, Ubn´, and Ucn´ is directly controlled by the ac output of the individual multi-level H-bridge cells. Considering the same dc voltage value Udc,HB = Udc/8 for each cell, according to equation 3-30, the phase output voltage Uxn´ of the 9L-SC2LHB VSC, e.g.
( )( )
, , 1 , 2 , 3 , 4 , 1 , 2 , 3 , 4
, , 1 , 2 , 3 , 4 , 1 , 2 , 3 , , 4
2 > , , , , , , ,
3 8 > , , , , , , , <
dc con x tri L tri L tri L tri L tri R tri R tri R tri R
dc con x tri L tri L tri L tri L tri R tri R tri R con x tri R
dc
xn
U if U U U U U U U U U
U if U U U U U U U U U U
U
U ′
⎡ ⎤⎣ ⎦
⎡ ⎤⎣ ⎦
=
( ), , 1 , 2 , 3 , 4 , 1 , 2 , , 3 , 4
, , 1 , 2 , 3 , 4 , 1 , , 2 , 3 ,
4 > , , , , , , < ,
8 > , , , , , < , ,
con x tri L tri L tri L tri L tri R tri R con x tri R tri R
dc con x tri L tri L tri L tri L tri R con x tri R tri R tri R
if U U U U U U U U U U
U if U U U U U U U U U U
⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
⎡ ⎤⎣ ⎦( )( )
4
, , 1 , 2 , 3 , 4 , , 1 , 2 , 3 , 4
, , 1 , 2 , 3 , 4 , 1 , , 2
0 > , , , , < , , ,
8 < , , , , , > ,
con x tri L tri L tri L tri L con x tri R tri R tri R tri R
dc con x tri L tri L tri L tri L tri R con x tri R tri
if U U U U U U U U U U
U if U U U U U U U U U
⎡ ⎤⎣ ⎦
⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦
⎡ ⎤− ⎣ ⎦( )( )
, 3 , 4
, , 1 , 2 , 3 , 4 , 1 , 2 , , 3 , 4
, , 1 , 2 , 3 , 4 , 1 , 2 , 3
,
4 < , , , , , , > ,
3 8 < , , , , , , ,
R tri R
dc con x tri L tri L tri L tri L tri R tri R con x tri R tri R
dc con x tri L tri L tri L tri L tri R tri R tri R co
U
U if U U U U U U U U U U
U if U U U U U U U U U
⎡ ⎤⎣ ⎦
⎡ ⎤ ⎡ ⎤− ⎣ ⎦ ⎣ ⎦
⎡ ⎤− ⎣ ⎦( )( )
, , 4
, , 1 , 2 , 3 , 4 , 1 , 2 , 3 , 4
>
2 < , , , , , , ,
n x tri R
dc con x tri L tri L tri L tri L tri R tri R tri R tri R
comprises nine voltage levels, viz. ±Udc/2, ±3Udc/8, ±Udc/4, ±Udc/8, and 0 (see Figure 3-41b and Table 3-19). The line-to-line output voltages of the 9L-SC2LHB VSC comprise seventeen voltage levels, viz. ±Udc, ±7Udc/8, ±3Udc/4, ±5Udc/8, ±Udc/2, ±3Udc/8, ±Udc/4, ±Udc/8, and 0 (see Figure 3-41c and Table 3-19). The load phase voltage Uan of the 9L-SC2LHB VSC comprises 29 voltage levels (see Figure 3-41d and Table 3-19).
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 57
Figure 3-40 Pulse width modulation for the 9L-SC2LHB VSC: (a) control signals Ucon,a and
58 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-41 Voltage waveforms of the 9L-SC2LHB VSC: (a) reference and triangular signals,
(b) output phase voltage Uan´, (c) output line-to-line voltage Uab, (d) output load-phase voltage Uan (mf = 15)
The spectrum of the phase and line-to-line output voltage waveforms are depicted in Figure 3-42a and Figure 3-42b respectively (at 1 15am .= and 15fm = ). As can be seen in these Figures, the first carrier band of the output voltages is centred around eight times the carrier frequency (f1Cb = 8fC), according to equation 3-33.
Udc
-Udc
0
(a)
(b)
(c)
(d)
0 90° 180° 270° 360°
Udc/2
0
Udc/4
-Udc/2
-Udc/4
Udc
0
Udc/2
-Udc
-Udc/2
3Udc/5
0
2Udc/5
Udc/5
-Udc/5
-2Udc/5
-3Udc/5
Uan
Uab
Uan´
Uan´ ,1
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 59
Figure 3-42 Harmonic spectrum of the phase voltage Uan´ (a) and the line-to-line voltage Uab (b) of the 9L-SC2LHB VSC
3.4.4. N-Level Series Connected 3-Level H-Bridge Voltage Source Converter (NL-SC3LHB VSC) [47], [120]
The topologies summarized above constitute the basic structures of the multi-level converters. To reduce the number of separate dc sources for high-voltage high-power applications, the SC2LHB VSC can be modified by replacing its conventional two-level converters (2L-H-Bridge) with combinations of multi-level converters (3L-H-Bridge). These combinations can be considered as having NL-SC3LHB VSC because this includes multi-level cells as the building block of the cascaded converter. Figure 3-43 represents the structure of the NL-SC3LHB VSC, utilizing p 3L-H-Bridge cells in series per phase leg. The dc link voltage depends on the number of the series connected 3L-H-Bridges and is determined by
3dc dc , L HBU p U −= × (3-46)
Using the same dc link voltage for each H-bridge cells Udc,3L-HB, the converter synthesizes an output phase voltage (e.g. Uan´, Ubn´, Ucn´)
1xn xn pxnU U ... U′ ′ ′= + + (3-47)
with a number of output phase voltage levels
4 1N p= + (3-48)
Due to a higher number of voltage levels, compared to the SC2LHB VSC, this converter generates an output voltage with improved harmonic performance.
The advantage of the topology is that it needs less separate dc sources. However, the modulation is more complicated due to the 3L-H-Bridge structure.
mf = 15, ma = 1.15
10-2
10-3
10-1
100
Har
mon
ic M
agni
tude
(p.u
.)
( )ab h
dc
UU
1 mf 2mf 3mf 4mf 5mf 6mf 7mf 8mfHarmonic order
mf = 15, ma = 1.15
Har
mon
ic M
agni
tude
(p.u
.)
10-2
10-3
10-1
100
( )′an h
dc
UU
1 3 mf 2mf 3mf 4mf 5mf 6mf 7mf 8mf
60 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-43 NL-SC3LHB VSC with p series 3L-H-Bridge cells per phase
3.4.4.1. Circuit Configuration of Five-Level Series Connected 3-Level H-Bridge Voltage Source Converter (5L-SC3LHB VSC)
The circuit of Figure 3-44 shows the basic topology of a single-phase 5L-SC3LHB VSC [46], [47], [120]. This converter was constructed from two halves of a three-level diode-clamped converter connected to the same bank of series capacitors to form a five-level converter. This topology is presently being produced by ABB and General Electric in their medium voltage (4160V) drive product [12], [46]. It contains 8 unidirectional active switches with inverse
a
b
c
0
3 ∼
n′
nph,ai
panU ′
pbnU ′
pcnU ′
1bnU ′
1cnU ′
abU
anU
pα
3
12p aS22p aS
11p aS21p aS
11p aS21p aS
12p aS22p aS
pα
3
12p bS22p bS
11p bS21p bS
11p bS21p bS
12p bS22p bS
pα
3
12p cS22p cS
11p cS21p cS
11p cS21p cS
12p cS22p cS
1anU ′1α
3
112aS212aS
111aS211aS
111aS211aS
112aS212aS
1α
3
112bS212bS
111bS211bS
111bS211bS
112bS212bS
1α
3
112cS212cS
11cS221cS
111cS211cS
112cS212cS
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 61
diodes and 4 neutral point clamp diodes per phase. If a NPC single-phase (3L-H-Bridge) replaces the conventional full-bridge cell (2L-H-Bridge), the voltage level is effectively doubled for each cell. Thus, to achieve the same voltage levels N for each phase, only (N-1)/4 separate dc sources are needed for one phase leg converter, whereas (N-1)/2 separate dc sources are needed for the NL-SC2LHB converter.
Although the converter in Figure 3-44 is a five-level structure, the concept may be expanded to any odd number of voltage levels [33]. Using the same philosophy, a full-bridge five-level phase leg can be built, based on the three-level flying capacitor topology, but in this section only the 5L-SC3LHB diode-clamped converter will be discussed.
3.4.4.2. Switch States and Commutations By suitably switching the converter transistors, the points a and n´ in Figure 3-44 may be connected to any of the points M0, M1, and M2 [33]. In order to produce five levels in each cell, the switches are controlled like in the conventional 3L-NPC VSC, which was explained in section 3.2.1.1.1. Four of the eight switches in each cell are turned on at any time. The switch positions for five possible states of each cell are given in Table 3-20, where 1 and 0 designate the on- and off state of the respective switch.
Assuming that the dc voltage is set to Udc and each capacitor remains charged to half of the dc voltage, the converter output voltage Uan´, according to equation (3-46), may be set to the five distance levels ±Udc, ±Udc/2, and 0 (Table 3-20). Capacitor voltage balancing in this topology may be accomplished in a straightforward way through redundant state selection [41]. As can be seen in Figure 3-44, switching to output voltages of ±Udc and 0 will not result in a current draw from the neutral point M1 and therefore will not affect the capacitor voltage balance. However, when a voltage of ±Udc/2 is required, the neutral junction will be utilized. As an example of how the redundant state switching is accomplished, consider the case where an output voltage of Udc/2 is desired and the phase current is positive. One possibility is to switch point a to junction M2 and point n´ to M1. This choice will tend to charge the lower capacitor since the current is flowing into the neutral junction. The other possibility is to switch point a to junction M1 and point n´ to junction M0. This will result in a current out of the neutral junction which will discharge the lower capacitor. The choice can then be readily made, depending on whether the lower capacitor is under- or over-charged relative to the upper one.
Udc,3L-HB
a
n´
C2
C1
Uc2
Uc1
idco
idc1
idc2M2
M0
Uan´
M1
111aS211aS
112aS212aS
111aS211aS
112aS212aS
12aD
11aD
22aD
21aD
62 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The commutation processes between the different switch states are the same as in the conventional 3L-NPC VSC, which was explained in section 3.2.1.1.1.
The distribution of the conduction and switching losses are summarized in Table 3-21 and Table 3-22 respectively. It is remarkable that four semiconductors lie within the current path in any switch state, either four active switches or four diodes.
Table 3-20 Switch positions for the 3L-H-Bridge converter
Table 3-21 Conduction losses in the 3L-H-Bridge converter
Table 3-22 Switching losses in the 3L-H-Bridge converter
3.4.4.3. Sine-Triangle Modulation
Gate signals for one half-bridge are produced by comparing one control voltage waveform with two triangular voltage waveforms tri ,upU and tri ,lowU (which is drawn for 15fm = ), as shown in Figure 3-45a. The upper and lower carrier band are in phase but displaced vertically. However, the triangular signals in each carrier band are shifted by TC/2 with respect to each other.
In order to trigger the switches, the following algorithm can be used. The comparison of Ucon with Utri,up,a and Utri,low,a results in the following logic signals to control the switches in the first leg
<( )con tri ,low,a con tri ,low,b ab dcand U U and U U U U
⎧⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪
< > ⇒ = −⎪⎩
(3-52)
comprise five voltage levels, viz. ±Udc, ±Udc/2, and 0 (see Figure 3-45f). The output voltage waveforms of the 5L-SC3LHB VSC according to Figure 3-44 are depicted in Figure 3-45.
The harmonic spectrum of the output voltage Uab is illustrated in Figure 3-46 (which is drawn for 15fm = ). It can be seen in this Figure that the first carrier band of the output voltage is centred around two times the carrier frequency (f1Cb = 2fC), according to equation 3-33.
64 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
Figure 3-45 Voltage waveforms of the 5L-SC3LHB VSC: (a) control signal Ucon and triangular
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES 65
Figure 3-46 Harmonic spectrum of the 5L-SC3LHB VSC
3.4.5. Conclusion Multi-level converters are becoming more attractive in high voltage and high efficiency applications. Because of their multi-step output voltage waveforms, the total harmonic distortion (THD) of the multi-level converter voltages is relatively low compared to the 2L-VSC. Moreover, the effective switching frequency of the multi-level converters is a function of its number of voltage levels. In other words, to achieve the same voltage THD, a higher-level converter can operate at a lower switching frequency. Obviously, the theoretical superiority of a multi-level converter is proportional to its number of voltage levels assuming ideal switches. However, the number of voltage levels is limited by its control complexity, complication of the system structure, cost and conduction losses.
Four multi-level VSCs have been considered: Neutral Point Clamp (NPC), Flying Capacitor (FLC), Series Connected Two-Level H-Bridge (SC2LHB), and Series Connected Three-Level H-Bridge (ML-SC3LHB). These converter topologies are compared in terms of the structure, function and basic characteristics in medium voltage applications. The number of components needed in each system is compared in Table 3-23, where N is the number of voltage levels. Clamping diodes are not required in the FLC and SC2LHB, while balancing capacitors are not needed in the NPC and FLC.
In the FLC topology, a high amount of capacitances are required for high voltage levels. In the 7L-FLC VSC, for example, 15 clamping capacitors plus 6 dc link capacitors are necessary to achieve the same voltage rating yielded by utilizing 9 capacitors in the SC2LHB topology. Not only do these many capacitors make the system less cost-effective, but they also induce the necessity to balance the capacitor voltages.
Figure 3-47 shows the total required components of Table 3-23 in four investigated multi-level converters as a function of the number of voltage levels. Although the same number of modules (IGBTs/diodes) is needed in the four considered topologies, the total number of components necessary in these four topologies is different at higher voltage levels. In the same voltage range, the NPC requires substantially more components than the others do; therefore, it does not qualify for the use with a high number of voltage levels. Moreover, for more than three-level configuration, the NPC voltage imbalance problem cannot be overcome by utilizing modulation techniques. Complex balance circuits would be necessary. This makes the NPC unattractive for levels larger than three.
As shown in Figure 3-47, to synthesize the same number of voltage levels, the SC2LHB
Har
mon
ic M
agni
tude
(p.u
.)mf = 15, ma = 1.15
( )ab h
dc
UU
10-3
1 3 mf 2mf 3mfHarmonic Order
100
66 BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
requires the least number of total main components. However, the SC2LHB needs more capacitors as compared to those needed in the NPC.
Another major advantage of the SC2LHB is its circuit layout flexibility, because each level has the same structure and there are no extra clamping diodes or voltage balancing capacitors, which are required in the NPC and the FLC topologies. The number of output voltage levels can then be easily adjusted by changing the number of H-bridge cells. Moreover, redundancy can be easily applied to enhance the reliability of the entire system. However, the control complexity is directly proportional to the number of H-bridge cells. As the number of voltage levels increases, the voltage imbalance problem becomes more of a concern. To achieve stable system, a well-defined model and an effective dc link balancing method are necessary.
Each cell of the SC3LHB VSC generates a number of output voltage levels higher than the SC2LHB VSC with fewer harmonic. To achieve the same number of voltage levels N for each phase, the SC3LHB requires a 3(N-1)/2 pulse-transformer, whereas a 3(N-1) pulse-transformer is needed for the SC2LHB VSC.
In conclusion, among the considered multi-level converter topologies, the Series Connected H-Bridge Converter is an attractive topology for multi-level converters.
Figure 3-47 Number of total components required in the multi-level converter as a function of
the number of phase voltage levels
Table 3-23 Comparison of power component requirements for multi-level topologies
Topology NPC FLC SC2LHB SC3LHB Number of module (IGBT/Diode) 6(N-1) 6(N-1) 6(N-1) 6(N-1) Number of clamping diodes 3(N-1)(N-2) 0 0 3(N-1) Number of dc link capacitors (N-1) (N-1) 3(N-1)/2 3(N-1)/2 Number of balancing capacitors 0 3(N-2) 0 0
Total 3N2-2N-1 N = 3, 4,…
10N-13 N = 3, 4,…
15(N-1)/2 N = 5, 7, 9,..
21(N-1)/2 N = 5, 9,…
3 4 5 6 7 8 90
30
60
90
120
150
180
210
240
Number of phase voltage levels
Num
ber o
f tot
al c
ompo
nene
ts
NPCFLCSC2LHBSC3LHB
4. MODELLING AND SIMULATION
This chapter introduces the modelling of the medium voltage drive components, including utility grid, load, multi-pulse transformer, rectifier, dc link capacitor, power semiconductor devices, and inverter, as shown in Figure 4-1.
Figure 4-1 Block diagram of Medium Voltage Drives: (a) NPC and FLC VSCs, (b) SCHB VSC
4.1. Load and Grid Models
4.1.1. Load Model The electric load component has different characteristics according to the variation of voltage and frequency. Thus, for proper operation, it is essential to model it.
Figure 4-2 depicts a standard load model for a one-phase and a three-phase form [5]. The simplified circuit diagram is based on the following conditions and simplifications:
• The three-phase equivalent circuit is assumed to be symmetric.
• It is accepted that the electromotive force (EMF) delivers sinusoidal voltages with variable amplitude and frequency.
DC-linkCapacitor
Grid Multi-PulseTransformer
Converter Load
is3
3
3
3
iL
Rectifier Inverter
(a)
is3
3
3
3
iL3
3
3
(b)
68 MODELLING AND SIMULATION
Figure 4-2 Standard load model for one-phase and three-phase
• Resistance RL is assumed to be zero. According to this assumption, the inductive portion LL of the load impedance is dominant.
Generally, this simplification is permissible for middle and large power drives, since the amount of the relationship between the inductive and resistive portion of impedance can be 10 and more for the nominal frequency of the converter. However, the simplification is invalid if the control of the converter is concerned. In particular, within very low fundamental frequency, for example, in the starting range of a drive, resistance RL is dominant in relation to inductor LL.
If the standard load is used with a star connection, the load voltages are equal to the phase voltages and the load currents are equal to the phase currents. However, it is not relevant to the converter which kind of load connection is used.
These general load models are often used to simulate an induction motor or a synchronous motor, which are the most important class of the three-phase loads. Although for simulation purposes, other simple load models are also considered such as an ideal current source or a series resistive-inductive load.
4.1.2. Grid Models The three-phase utility grid is modelled by an electrical generator that implements a symmetrical voltage of three different phases (e.g. UsA, UsB, UsC) with internal resistive-inductive impedance. In contrast to the load model, the currents are defined to be positive in the inverse direction according to Figure 4-3. The three voltage sources are connected in star with a neutral connection that can be internally grounded or made accessible. The source-internal resistance Rs is assumed to be zero.
Figure 4-3 Standard three-phase utility grid model
4.2. Converter Model
4.2.1. Inverter The inverter consists of the power semiconductor devices which are triggered by sine-triangle modulation scheme.
iLa RL LLea
Ua
iLa RL LL
iLb RL LL
iLc RL LL
ea
eb
ec
Ua
Ub
Uc
isARsLs
isBRsLs
isCRsLs
UsA
UsB
UsC
MODELLING AND SIMULATION 69
4.2.1.1. Modulation method The modulation is one of the important factors in optimizing the performance of the converter. The modulation process determines the spectral content of the output waveforms as well as the distribution of losses within the converter. Many different modulation approaches have been proposed in the literature [43], [53], [56], [68], [69], [70], [71]. The converter model in this thesis is based on the sine-wave modulation strategy with a third harmonic added, as explained in detail in chapter 3 and Appendix.
4.2.1.2. Compact Power Semiconductor Model In this thesis, IGBT modules are considered due to the modularity. For analysis purposes, the IGBTs and diodes are usually considered ideal, i.e. lossless, featuring infinite current and voltage handling capability according to Figure 4-4. The ideal IGBT is simulated as being controlled by a logical gate signal (gs ≥ 0). It conducts an arbitrary current with zero on-state voltage when the switch is on (gs > 0) and blocks any forward or reversely applied voltage with zero current when the switch is off (gs = 0) [4]. The device can be switched instantaneously between on and off states or vice versa by triggering it.
Figure 4-4 The ideal circuit symbol of the IGBT
4.2.1.2.1. Power Semiconductor Losses For the calculations, the load current is assumed to be an ideal sinusoid. Then, a symple calculation of the power semiconductor losses for medium voltage converters is presented.
The losses of an IGBT can be classified as switching losses and on state (conduction) losses.
The power loss dissipation in an IGBT (Ploss,T) and diode (Ploss,D) can be calculated as
( )loss ,T CE ,n C ,n C on offC
turn-on and turn off losses on-state loss
tP U I f E ET⎡ ⎤ ⎡ ⎤= ⋅ ⋅ + ⋅ +⎢ ⎥ ⎣ ⎦⎣ ⎦
(4-1)
[ ]1loss ,D F F ,n C recC Reverse recovery loss
on-state loss
tP U I f ET
⎡ ⎤⎛ ⎞= − ⋅ ⋅ + ⋅⎢ ⎥⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦
(4-2)
with
UCE,n is the on state saturation voltage and IC,n is the collector current of the IGBT UF,n is the on state voltage and IF,n is the forward current in the diode fC is the carrier frequency and TC is the one period of the carrier frequency Eon is the turn-on and energy and Eoff is the and turn-off energy of the IGBT and Erec is the recovery energy in the diode.
These parameters may be deviated from the data sheets.
IC
UCE
70 MODELLING AND SIMULATION
4.2.1.2.2. Loss Approximation based on Datasheets A loss model of the device is developed based on an experimental determination of the power losses. The total power losses in the converter are estimated to determine the junction temperature.
A. Conduction Losses The conduction losses Pcon,x of an IGBT or a diode can be expressed by the well-known approximation as [29], [66], [143]
( )( ) ( )1
01
1 con ,xT B
con,x o ,x con,xP U A i t i t dtT
= + ⋅ ⋅ ⋅∫ (4-3)
with
Pcon,x are the conduction losses in device x T1 is the fundamental period Uo,x and Aon,x are on state voltage parameters for device x Bcon,x is the curve-fitted constant for device x and i is the instantaneous value of the device current.
B. Switching Losses Switching losses are created by the commutation processes between different switch states. These commutation processes can be classified into (1) natural or inductive commutations, which are characterized by turn-on losses of active switches and recovery losses of diodes, and (2) forced or capacitive commutations, which are contrarily characterized by turn-off losses of active switches. Turn-on losses of diodes are usually small and can be neglected [1], [3].
It is possible to calculate the switching losses on the basis of the collector-emitter voltage and the collector current. However, this is not a very accurate method due to the need of rough approximations. Therefore, it is more effective and more accurate to measure the switching energy directly as a function of the load current and then describe the relationship by a simple equation. The equation
Esw,x is the switching energy loss for device x, Asw,on,x, Bsw,on,x and Asw,off,x, Bsw,off,x are turn-on and turn-off curve-fitting constants for device x, Ucom is the commutation voltage, and UCE denotes the voltage at which the losses where measured.
This equation is useful for turn-on and turn-off losses of the IGBT as well as for the diode. The constant parameters are determined by applying a first-order curve-fitting of the measured on state voltage characteristics and the switching energy losses which are dependent on the load current. The fitting parameters and thermal resistances of the semiconductors examined in this thesis are given in Table 4-1 [29], where the abbreviations T (IGBT) and D (Diode) are used for a device x.
Therefore, the average switching losses Psw,x are written as
1
01
1 T
sw,x sw,xP E dtT
= ⋅∫ (4-5)
MODELLING AND SIMULATION 71
The total converter losses are dependent on the conduction ratio of the diode and the IGBT (modulation index ma and power factor cosϕ) on the modulation method, the junction temperature Tj, dc link voltage Udc, gate drive conditions, load current, and switching frequency fC [66].
Table 4-1 Fitting parameters and thermal resistances of medium voltage IGBTs/Diodes
C. Selection of Heat Sinks For safe operation, the power losses generated by each module must be dissipated. The heat transfer of a semiconductor can be simulated in an electric circuit. Figure 4-5a shows the general equivalent circuit for an IGBT module. At steady state the junction temperature Tj can be calculated using the following thermal equation
( ) loss th,ch th ,ha loss ,x th, jcx aj xT P R R P R T= × + + × + (4-6)
with
Rth,jc denotes the thermal resistance of the IGBT/diode from junction to case Rth,ch is the thermal resistance of the IGBT/diode from case to heat sink Rth,ha is the thermal resistance from heat sink to ambient, and Ta is the ambient temperature.
Infineon/Eupec published a new datasheet software for IGBT modules in 2003 [147] which states that Rth,ch can be supplemented by the therein included values for Rth,chT and Rth,chD, as shown in Figure 4-5b. However, homogeneous heat distribution to the base plate is not guaranteed under all operation conditions [147] due to the distribution of separate chips for the IGBT and diode across the module’s surface. Hence, a separate thermal calculation for the IGBT as well as the diode part is necessary. The values of Rth,chT and Rth,chD can already be derived from the previous specification but have now been added for more simplicity, as shown in Table 4-2 taken from [147].
Figure 4-5 The steady state equivalent thermal circuit diagram: (a) general model, (b)
Infineon model
Table 4-2 Thermal resistance of the IGBT module: FZ600R65KF1 [147]
4.2.1.2.3. Description of the Loss Simulation Model [66], [143]
An accurate loss simulation model, which is described in detail in [3], [22], [66], enables the determination of the semiconductor losses and junction temperatures. The accuracy of the loss and junction temperature calculation and the thermal model being applied is evaluated in [3], [29], [66]. To calculate the ideal current rating IC,n (IF,n), an ideal parallel connection of commercially available IGBT or diode modules is assumed. It is obvious that on state and switching losses are adapted to the ideally rated current and the corresponding silicon area, as shown in Figure 4-6. Furthermore, the thermal resistances Rth,jc and Rth,ch are adjusted to the rational number of ideally parallel connected modules according to the silicon area and the module size.
4.2.1.2.4. Agreement Calculation Measurement An agreement calculation of the power semiconductor on-state voltage and switching losses is represented at this stage. It is necessary to use computer simulations in order to realize detailed
Previous specifications Thermal resistance, case to heat sink per module Rth,ch 6K/kW
New specifications Thermal resistance, case to heat sink per module Rth,ch 6K/kW Thermal resistance, case to heat sink per IGBT Rth,chT 9K/kW Thermal resistance, case to heat sink per Diode Rth,chD 18K/kW
Tj(T)
Tj(D)
Rth,jcT
Rth,jcDRth,ch Rth,haPloss,T
Ploss,D
Junction
Ta
Case Heat sink Ambient
(a)
Rth,jcT
Rth,jcD
Rth,chT
Rth,ha
Junction Case Heat sink Ambient
Rth,chD
Ploss,T
Ploss,D
Tj(T)
Tj(D)
Ta
(b)
MODELLING AND SIMULATION 73
power loss calculations of different converter topologies. The output characteristics of the IGBT/diode modules have been approximated based on data contained in the module specification sheets.
Figure 4-7 depicts the simulation results for the FZ800R33KF2C IGBT-module from Eupec.
Figure 4-6 Characteristics of current sharing for two connected modules in parallel
Figure 4-7 Approximation characteristics based on the curve-fitting method: (a) IGBT/Diode on-state characteristics, (b) IGBT turn-on and IGBT/Diode turn-off switching energy (FZ800R33KF2C IGBT-module from Eupec, UCE = 1800V, Tj,max = 125°C)
4.2.2. DC Link Capacitor Models
The instantaneous dc link current values of the grid side and the machine side converter are generally different. The dc link capacitor serves for the decoupling of both sides from each other. This section discusses the modelling process of a dc link capacitor.
4.2.2.1.1. Aluminium Electrolytic Capacitors [135], [138] Aluminium electrolytic or foil capacitors are generally used in converters to smooth the dc link voltage. Among the various types of capacitors, aluminium electrolytic capacitors offer a large volume at low cost. It can also provide a large capacitance, compared with other types. Hence, it is mostly used in low voltage converters. The principle structure of an aluminium electrolytic capacitor is represented in [13], [135] in detail.
The equivalent circuit of an aluminium electrolytic capacitor is shown in Figure 4-8 [135]. It forms a capacitance, a series resistance, a series inductance, and a parallel resistance. Equivalent Series Resistance (RESR) is the series resistance consisting of the aluminium oxide layer, electrolyte/separator combination, and other resistance-related factors, foil length, foil surface area, among others. It depends upon the temperature and represents the di-electric losses and the resistance of the electrolytes and the connections.
The series capacitance Cx represents the actual capacity of the capacitor and depends upon frequency and temperature. The capacitance of an aluminium electrolytic capacitor becomes smaller with increasing frequency. As the temperature decreases, the capacitance also becomes smaller.
The Equivalent Series Inductance (LESL) consists of the inductive resistance of the connecting cables. The bypass resistor REPR is due to a leakage current and can be neglected.
The capacitor is designed for an operating voltage UC. This may be exceeded only briefly by a peak voltage of 10 percent. All aluminium electrolytic capacitors are polarized for dc applications. Therefore, the alternating voltage may be located only within the range ≤ UC [135]. Each capacitor has a rating current which is effective at the maximal permissible alternating current. Typical values for an acceptable rating current range from 3mA to 22mA per µF [13], [136]. The capacity is indicated for a certain operating point. Typical tolerance values for the capacity are ±10% and ±20% for operating voltages of UC > 150V.
Aluminium electrolytic capacitors have a higher dissipation factor tanδ than any other types of capacitors. Therefore, the ripple current causes in aluminium electrolytic capacitors a higher internal heat. This leads to an increase in temperature.
Figure 4-8 Equivalent circuit of a capacitor [135]
4.2.2.1.2. Film Capacitors [139], [140] Since 1980, great improvements have been made on dc film capacitors. Their volume and weight have been reduced by a factor of 3 or 4 over the last years. By now, film manufacturers [140] have developed thinner films and improved the segmentation techniques. Today film capacitors are attractive in a voltage ranges between 600V DC and 1200V DC. Depending on the application, over 1200VDC, oil-filled versions are recommended [139]. Consequently, the
REPR
RESR LESLCx
MODELLING AND SIMULATION 75
trend of industrial and traction power conversion is to replace electrolytic capacitors with film technology. This trend is supported by the many advantages that film technology offers [140]. These include: high effective current capabilities up to 1ARMS per µF, over-voltage withstanding up to 2 times the rated voltage, capability of voltage reversal and high peak current, no acid inside, long lifetime, and no storage problems. The principle structure of film capacitors is represented in [139] in detail.
Film capacitors have the same simplified equivalent circuit as aluminium electrolytic capacitors, as depicted in Figure 4-8. However, the magnitude of the parameters differs strongly from that of the aluminium electrolytic capacitors. The serial inductance LESL and the serial resistance RESR are clearly smaller. Thus, the dissipation factor tanδ is also clearly smaller. It is typically in the range of 10-4...10-3, whereas for aluminium electrolytic capacitors it is in the range of 10-2...100.
The capacitance of the film capacitors remains virtually unaffected by the frequency up to 1MHz [139]. The frequencies of film capacitors are increased by 100 times, compared to the aluminium electrolytic capacitors, due to their structure. The capacity of film capacitors depends on the temperature and exhibits a small tolerance compared to aluminium electrolytic capacitors [139]. The capacitance fluctuation as a function of temperature is smaller than that in the aluminium electrolytic capacitors. The temperature range is typically from -55°C ... 85°C with a variable capacity of -4% ... +2%.
The maximum continuous voltage of film capacitors is equal to the rated dc voltage, and their maximum permissible current rating depends on the energy dissipation.
The film capacitors are outstandingly suitable for high alternating current applications because of their small dissipation factor and self-heating. Typical values for film capacitors are from 150 to 250mA per µF rated current, up to 1000V rated voltage, and 1mF nominal capacity. However, film capacitors are relatively expensive compared to aluminium electrolytic capacitors.
For simulation purposes, two simplified capacitor models have been used. In the first model, the effect of REPR, LESL, and RESR is neglected. The second model which was applied is an ideal voltage source.
4.2.3. Rectifier Models
In medium voltage drives, a diode rectifier is often used as a front-end converter due to its simple structure and low manufacturing cost. The simplified circuit diagram of the standard six-pulse rectifier is represented in Figure 4-9. To simplify the simulations, all the diodes are considered to be ideal, i.e. without any on state voltage drops, reverse recovery behaviour or power losses.
Figure 4-9 Circuit diagram of the standard six-pulse diode rectifier
idc
UuUvUw
Udc
76 MODELLING AND SIMULATION
4.3. Isolation Transformer Modelling and Simulation [6], [7], [9], [67] The dc power supplies are made of rectifiers which inject harmonics into the grid. Increasing the pulse number of the rectifiers (e.g. 12-, 18-, 24-pulse rectifier) is attractive, since the grid current harmonics decrease. Corresponding circuit configurations are shown in Figure 4-10. This requires phase-shifting transformers with multi-windings. The 15-degree phase shift can not be obtained by classical transformers with delta, star, or zigzag winding connections. The only means is using an unbalanced zigzag winding with two different numbers of turns. The most complex part of modelling such special transformers is the determination of all the needed parameters: inductance and resistance values for each winding and coupling coefficients between all considered windings. These parameters must be determinated by using the measurements obtained from the typical tests under no-load and short-circuit conditions. Unfortunately, perfect transformers cannot be built in practice. The output voltage of the secondary windings cannot be perfectly balanced because this depends on turn ratios, which are limited to plus or minus one turn. Leakage reactance is another function of the coil position and volume.
Therefore, the perfect balance between the groups of secondary windings cannot be achieved. However, to simplify the analysis the simulations are performed under the assumption of balanced three-phase line voltages.
Figure 4-10 Multi-pulse phase-shift transformer
4.3.1. Transformer Model The 24-pulse isolation transformer is designed to provide one-fourth of the nominal input voltage to each of the four rectifiers at a 15-degree phase displacement from each other. The 15-degree phase shift is obtained by phase shifting the transformers secondary windings. Some transformer connections can be used to achieve the 15-degree phase displacement between the input voltages and the four rectifiers. Figure 4-11 depicts two typical diagrams of 24-pulse
transformers constructed from two 12-pulse transformers. Each model has six windings overall, two windings in the primary sides and four windings in the secondary sides.
Figure 4-11b shows the model which is used by the industry with zigzag primary connections and a delta-star connection in the secondary sides; whileFigure 4-11a simply uses an isolation transformer with a delta-primary connection and four zigzag secondary winding connections, one shifted +22.5 degrees, one shifted -7.5 degrees, one shifted +7.5 degrees, and one shifted -22.5 degrees in relation to the primary connection.
The transformer has a turn ratio that ensures the total dc voltage produced by the four rectifiers being the same as that of a single unit of the three-phase diode rectifier directly connected to the utility grid.
Due to the use of diode rectifiers, the secondary currents are distorted, but they do not contain even or triple harmonics if a constant dc link current is assumed. The secondary currents can be expressed as
The utility grid phase current sAi (Figure 4-17) can be calculated by
1 2 1 2 3 4' ' ' '
sA p p s s s si I I I I I I= + = + + + (4-11)
where 1 2 3 4' ' ' '
s s s sI ,I ,I ,I are the secondary currents referring to the primary side. For the referred current 1
'sI , all the positive-sequence current components (h = 1, 7, 13, 19 …) are 22.5° ahead
of their corresponding positive-sequence currents whereas all the negative-sequence components (h = 5, 11, 17, 23…) are -22.5° behind their counterparts in the secondary winding.
The magnitude of this current is reduced by the turn ratio of the transformer trn ; therefore
( ) ( )11 7 13 19 5 1117 23
1 22 5 22 5 22 5 22 5's h h
h , , , ,... h , , , ,...tr
I I sin h t h . . I sin h t h . .n
ω ω∞ ∞
= =
⎡ ⎤= + × ° − ° + + × ° + °⎢ ⎥
⎣ ⎦∑ ∑ (4-12)
In a similar method, the other referred currents 2 3 4' ' '
s s sI ,I ,I can be expressed as
( ) ( )21 7 13 19 5 1117 23
1 7 5 7 5 7 5 7 5's h h
h , , , ,... h , , , ,...tr
I I sin h t h . . I sin h t h . .n
ω ω∞ ∞
= =
⎡ ⎤= − × °+ ° + − × °− °⎢ ⎥
⎣ ⎦∑ ∑ (4-13)
( ) ( )31 7 13 19 5 1117 23
1 7 5 7 5 7 5 7 5's h h
h , , , ,... h , , , ,...tr
I I sin h t h . . I sin h t h . .n
ω ω∞ ∞
= =
⎡ ⎤= + × °− ° + + × °+ °⎢ ⎥
⎣ ⎦∑ ∑ (4-14)
( ) ( )41 7 13 19 5 1117 23
1 22 5 22 5 22 5 22 5's h h
h , , , ,... h , , , ,...tr
I I sin h t h . . I sin h t h . .n
ω ω∞ ∞
= =
⎡ ⎤= − × ° + ° + − × ° − °⎢ ⎥
⎣ ⎦∑ ∑ (4-15)
in which the first term represents all the positive-sequence harmonic currents while the second term denotes the negative-sequence harmonic currents.
Substituting equations (4-12) through (4-15) with (4-11) and using an appropriate turn ratio yields
[ ]1 2 3 4 1 23 2523 25' ' ' 'sA s s s si I I I I I sin t I sin t I sin t ...ω ω ω= + + + = + + + (4-16)
Equation (4-16) shows that the low-order current harmonics, 5th, 7th, 11th, 13th, 17th, and 19th are eliminated due to the transformer connection, and they do not appear in the utility grid current. The other harmonic components (up to the 49th) and their corresponding phase angles are also calculated and listed in Table 4-3. As a result, the utility line current is close to sinusoidal with little distortion, which is recommended by the IEEE standard 519-1992 [151] and C57.135-2001 [152].
MODELLING AND SIMULATION 79
Table 4-3 Harmonic current and their phase angles in 24-pulse transformers
4.3.1.1. Transformer Winding Model
Generally, in high power applications, using two transformers is more favourable and the mechanical construction is simpler, compared to one transformer with four secondary windings. In this section, two different configurations are modelled and investigated, according to Figure 4-11a and Figure 4-11b, applying the transformer component in MATLAB/PLECS. It should be noted that the kind of winding connections is the basic difference between these configurations.
In the first model Dzz, two basic zigzag couplings are used for negative and positive phase shifts, as shown in the left part of Figure 4-12a. In the second model Zdy, which is used by the industry, the zigzag primary connections and delta-star secondary connections are used for the desired phase-shift angle, as shown in the left part of Figure 4-12b. This means that the Zdy configuration needs thinner conductors due to more windings than the Dzz configuration. Therefore, the fluctuations on the primary windings are realized simpler in the Zdy configuration.
In the following sections, both configurations are investigated separately and finally the results are compared. Table 4-4 shows the necessary input data that corresponds to the data plate of the transformer used for both models.
Table 4-4 The necessary input data of the 12-pulse phase-shift transformer
Apparent rated power, SN1 2.25[MVA] Primary side line voltage, UN1 10[kV] Secondary line voltage (no-load), UN20 0.741×Udc,n[V] Frequency, f1 50[Hz] No-load primary side current, io @ 0.005[p.u.]
@ The no-load current of transformers with a range of 1 to 10MVA is assumed to about 0.9% of the rated current [6].
(Dzz), (b) Zigzag-delta-star configuration (Zdy) used by the industry
U11 V11 W11
U21 V21 W21
U22V22 W22
LU11D LV11D LW11D
LU21Y LV21Y LW21Y
LU21D LV21D LW21D
LV22Y LW22Y LU22Y
LV22D LW22D LU22D
U22V22 W22U21 V21 W21
U11
V11W11
U22
V22W22
U21
V21W21
-
Secondary 1, 3 Secondary 2, 4
U11 V11 W11
Primary 1,2
U´21 V´21 W´21 U´22V´22 W´22
(a)
U11 V11 W11
U22Y V22Y W22Y
LU22Y LV22Y LW22Y
U21D V21D W21D
LU21D LV21D LW21D
LU11Y LV11Y LW11Y
LU11D LV11D LW11D
U11 V11 W11
7.5°
U11
V11W11
U21D
V21D
W21D
-22.5° 7.5°
U22Y
V22Y
W22Y
U21D V21D W21D U22Y V22Y W22Y
Primary 1 Secondary 1 Secondary 2
U´11 V´11 W´11
LU12Y LV12Y LW12Y
LU12D LV12D LW12D
U24D V24D W24D
LU24D LV24D LW24D
U23Y V23Y W23Y
LU23Y LV23Y LW23Y
U12 V12 W12
Primary 2
U´12 V´12 W´12
-7.5°
U12
V12W12
Secondary 4
U24D V24D W24D
U24D
V24DW24D
22.5°
U23Y V23Y W23Y
Secondary 3
-7.5°
U23Y
V23YW23YU12 V12 W12
MODELLING AND SIMULATION 81
I. Delta-zigzag-zigzag (Dzz) configuration This configuration is represented in Figure 4-12a. For the secondary 1 winding, the desired phase-shift angle is equal to -22.5°. This means that this secondary winding has to be a combination of Dy11 (-30°) and Dd0 (0°) [67].
The secondary phase voltage is shown in Figure 4-13. For the negative or positive phase shift, the zigzag winding of each phase consists of three parts.
Figure 4-13 Windings position for positive (a), and negative (b) phase shift of Dzz configuration
Based on Figure 4-13a, the following equation can be written for the negative phase shift
( ) ( ) ( )21 21 21 21 21 21 21 21U V U U U V V V′ ′ ′ ′= − + − + − (4-17)
21 21 21 21 21 21 21 21U V U U U V V V→ → → →
′ ′ ′ ′= + + (4-18)
The turn ratios between the secondary windings n21YD can be calculated as
2021 21 21 21 21 2121
21 21 21 21 21 20 210 866 1 5N YY
YDD N D
Un U U V V tannn U V U V U . . tan
αα
′ ′ −= = = = =
′ ′ ′ ′ + (4-19)
where UN20Y, UN20D are secondary no-load voltages with star and delta connections in each three-phase transformer.
Now equation (4-18) can be rewritten as below by applying equation (4-19)
( ) ( )21 21 21 21 21 21 211 60 60YD YD YDU V U V n n cos j n sin→
′ ′= + + × ° − × °⎡ ⎤⎣ ⎦ (4-20)
( ) ( )2 2 2121 21 21 21 21 21
21
0 8661 1 5 0 8661 1 5
YDYD YD
YD
. nU V U V . n . n arctg. n
→ ⎛ ⎞− ×⎡ ⎤′ ′= + × + × ∠ ⎜ ⎟⎣ ⎦ + ×⎝ ⎠ (4-21)
21 21 21 21 21 21U V k U V α→
′ ′= × ∠ (4-22)
where k21 is a constant and calculated as
U´21
V´21W´21
LV21Y
LU21D
LU21Y
U21
W21
V21
-
U´22
V´22W´22
LW22Y
LV22D
LV22Y
U22
W22
V22(a) (b)
OO
82 MODELLING AND SIMULATION
( ) ( )2 22021 21 2121 21 21
21 21 20 21
1 1 5 0 866NYD YD' '
N D D
UU V nk . n . nU V U n
⎡ ⎤= = = = + × + − ×⎣ ⎦ (4-23)
The next step is to define the similar open-circuit turn ratio ntr between the primary and each secondary winding of the transformer.
111 11 11
21 21 21 20
Ntr
N
Un U Vnn U V U
= = = (4-24)
According to Figure 4-14, the equivalent short-circuit impedance for secondary winding j can be calculated as follows
( ) 2 21 2 2 1
1 1
1 1 4' '
' ' jD jYkj jD jD jY jD
jD jD
Z ZZ Z Z Z Z where j ,..,
Z Z
⎛ ⎞⎛ ⎞⎜ ⎟⎜ ⎟= + = + =
⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠ (4-25)
where 2
'
jDZ and 2
'
jYZ denote the secondary winding impedance with star and delta connections referred to the primary side, and Z1jD is the primary winding impedance.
Figure 4-14 Equivalent electrical circuit of a linear 3-winding transformer
With due attention to the winding impedance, which is proportional to the square number of windings turns, it can be written as
2 2 2 2 2 2
2 11 1 11 12
' ' '
'
jY jY jD jD jY jY
jD jD jDjD
n Z n Z n Z , ,
n n Z n ZZ= = = (4-26)
By substituting equations (4-24) and (4-26) in equation (4-25), the equation
( )2
21 2 2
21 2
11
jYDkj jD
jYD
nZ Z
k n
⎛ ⎞⎜ ⎟= +⎜ ⎟+⎝ ⎠
(4-27)
results.
Moreover, by suggesting a value for the transformer short-circuit voltage Uk = 10% [146], the equal short-circuit impedance can be calculated according to equation (4-28).
0 1kj k N NZ U Z . Z= × = × (4-28)
The absolute value is taken account of since a phase shift will be introduced in the zigzag
21 21j L Rω
11n
21n
22n
11 11j L Rω
22 22j L Rω
m mj L Rω1NU
21NU
22NU
21Z
22Z
11Z
MODELLING AND SIMULATION 83
winding. By replacing equation (4-27) in equation (4-28), the primary winding impedance can be calculated as
( )
11 2
22 2
2 2
0 1
11
N jjD
jYD
j jYD
. ZZ
nk n
×=
++
(4-29)
Now the equivalent circuit parameters include the winding resistance, the leakage inductance and the magnetizing impedance of the zigzag winding can be determined. These parameters are strongly dependent on the rated output current of the transformer. At large units in a range of 1MVA to 10MVA, the leakage inductance can be considered to be 20 to 30 times the resistance [6]. In order to determine the shares of the winding resistance and the leakage inductance in each transformer, a ratio of 25 is considered between the leakage inductance and the winding resistance (XT = 25RT). Then, the following equation can be used to determine the winding resistance and the leakage inductance in each transformer.
2
2
1
TT
T
T
ZR XR
=⎛ ⎞
+ ⎜ ⎟⎝ ⎠
(4-30)
1 1
202
T TT
X RL fω π
= = (4-31)
II. Zigzag-delta-star (Zdy) configuration This configuration is represented in Figure 4-12b. Two primary windings with the desired phase-shift angle of ±7.5° are considered. This means that the primary windings have to be a combination of Delta-star DY and Delta-delta DD connections. The primary phase voltage is shown in Figure 4-15. Similar to the secondary windings in the Dzz configuration, the primary zigzag winding of each phase consists of three parts for the negative or positive phase shift.
Figure 4-15 Windings position for positive (a), and negative (b) phase shift of Zdy configuration
(a)
U´11
V´11W´11
LU11Y
LV11D
LV11Y
U11
W11
V11
O
(b)
U´12
V´12W´12
LV12Y
LU12D
LU12Y
U12
W12
V12
-
O
84 MODELLING AND SIMULATION
Therefore, equations (4-19) and (4-23) can be rewritten for the positive phase shift, according to Figure 4-15a,
1011 11 11 11 11 1111
11 11 11 11 11 10 110 866 1 5
' 'N YY
YD ' ' ' 'D N D
Un U U V V tannn U V U V U . . tan
αα
= = = = =−
(4-32)
( ) ( )2 211 11 11
11
1 1 1 5 0 866YD YDD
k . n . nn
⎡ ⎤= = + × + ×⎣ ⎦ (4-33)
where UN10Y, UN10D are primary no-load voltages with star and delta connections in each three-phase transformer.
The same equations can be applied to the negative phase shift case, according to Figure 4-15b.
4.3.1.2. MATLAB/PLECS Implementation The MATLAB simulation software is used to simulate these multi-winding transformers in detail. Both Dzz and Zdy configurations are modelled, examined, and compared. The linear three-winding transformer in the PLECS models three coupled windings on the same core, which is a toolbax for the fast simulation of electrical and power electronics circuits, according to Figure 4-14. The magnetization inductance Lm and the core losses Rm are modelled as linear elements. The magnetization resistance Rm represents the core losses and is negligible in this part. Instead, the values of the core losses are referred to the primary side. For the following discussion, this equivalent electrical circuit is assumed for both Dzz and Zdy configurations. The following computation shows how to model a three-winding transformer with a zigzag connection in detail.
I. Dzz configuration By setting UN1 = 10kV and UN21 = 1200V as well as using equation (4-24), the open-circuit turn ratio between the primary and secondary windings can be calculated as
11
2
10000 8 33 1 41200tr
j
nn . where j ,..,n
= = = = (4-34)
By setting SN1 = 2.25MVA, the rated impedance ZN11Y of the primary winding is calculated according to equation (4-35)
( )[ ]
23 221
11 31
10 1044 44
2250 10N
N YN
VUZ .S VA
⎡ ⎤× ⎣ ⎦= = = Ω×
(4-35)
The star-connected equivalent no-load impedance Z11Yo is calculated by taking into account the no-load current io (Table 4-4) [67]
11 111 1 44.44 8.88
0.005oY N Yo
Z Z ki
= × = × Ω = Ω (4-36)
Using the angular frequency, the equivalent star-connected inductance LmY is calculated as
11 28 292 50
oYmY
ZL . H
Hzπ= =
× (4-37)
To obtain the delta-connected inductance LmD, the previous value has to be multiplied by 3; thus
MODELLING AND SIMULATION 85
3 28 29 84 88mDL . H . H= × = (4-38)
Considering a negative phase-shift angle of –22.5° and using equation (4-23), the ratio between the turn number of the star and delta connection of this secondary winding is equal to
Then, the turn number of the star and delta connections of this secondary is equal to
21 21 21 2121
1 0 261 0 442D Y D YDn . , n n n .k
= = = × = (4-41)
Now the equal short-circuit impedance Zk1 can be calculated as
1 110 1 4 44k N YZ . Z .= × = Ω (4-42)
Further, by using equation (4-29), the primary winding impedance is calculated as
( )114 44 4 23
1 0 05D.Z .
.Ω
= = Ω+
(4-42)
Now by applying equations (4-30) and (4-31), the primary winding resistance, the primary leakage inductance, and the primary impedance are calculated as
( ) ( )2
11 1124 23 200 211 0 211 0 0134
2 501 20D D
.R . , L . . H= = Ω = × =+ π
(4-44)
( )11 11 11 0 211 4 22D D DZ R jX . j .= + = + Ω (4-45)
Afterwards, the secondary winding resistance, the secondary leakage inductance, and the secondary impedance can be determined on the basis of equation (4-26), yielding the following equations
The same equations can be applied to the positive phase-shift case, according to Figure 4-13b. To achieve this aim, a similar method is employed for the positive phase-shift angle of 7.5°. The ratio between the turn number of the star and delta connections of this secondary winding is equal to
Then, the turn number of the star and delta connections of this secondary winding is equal to
22 22 22 2222
1 0 765 0 151D Y D YDn . , n n n .k
= = = × = (4-55)
Thus, by using equation (4-29), the primary winding impedance is calculated as
( )124 44 4 34
1 0 0219D.Z . .Ω
= = Ω+
(4-56)
Now by using equations (4-30) and (4-31), the primary winding resistance, the primary leakage inductance, and the primary impedance are calculated as
12 120 217 0 0138D DR . , L . H= Ω = (4-57)
( )12 12 12 0 217 4 33D D DZ R jX . j .= + = + Ω (4-58)
Then, the secondary winding resistance, the secondary leakage inductance, and the secondary impedance can be determined as follows, based on equation (4-26),
( )22 22 22 0 0713 1 42Y Y YZ R jX . j . m= + = + Ω (4-64)
Thus, the secondary equivalent impedance is equal to
MODELLING AND SIMULATION 87
( )22 22 223 2 40 7Y DZ Z Z j . m= × + = + Ω (4-65)
Now the primary equal impedance of parallel transformers (-22.5° and 7.5°) can be calculated by
( ) ( )( ) ( ) ( )11 11 12
0 211 4 22 0 217 4 330 108 2 14
0 211 4 22 0 217 4 33D D
. j . . j .Z Z Z . j .
. j . . j .+ Ω× + Ω
= = = + Ω+ Ω+ + Ω
(4-66)
Thereby, the magnetization inductance Lm is equal to
2 2 84 88 169 7m mDL L . H . H= × = × = (4-67)
Similar methods can be used to obtain the winding resistances, the leakage inductances, and winding impedances for the parallel operation of the negative phase-shift angle –7.5° and positive phase-shift angle 22.5°. Table 4-5 depicts the quantity results for all secondary windings in detail. These values are used directly in the PLECS model component of MATLAB.
As seen in Table 4-5, similar results are obtained for the secondary windings with a phase-shift angle of ±22.5° and a phase-shift angle of ±7.5° too. Therefore, the primary equivalent impedance of the parallel transformers -22.5° and 7.5° is equal to the primary equivalent impedance of the parallel transformers 22.5° and -7.5°
( )11 11 0 108 2 14'Z Z . j .= = + Ω (4-68)
Then, the primary equivalent impedance of transformer Z1 is equal to
( )1 11 11 111 0 54 1 072
'Z Z Z Z . j .= = = + Ω (4-69)
Table 4-5 The secondary quantity parameters for the 24-pulse transformer with Zdy connection
II. Zdy configuration The Zdy configuration parameters can be determined like the Dzz configuration. For this purpose, the following model is assumed for each 12-pulse transformer, according to Figure 4-16.
The calculations are accomplished on the basis of equations (4-19) to (4-31) and the input data of the Table 4-4. The computation results are summarized in Table 4-6.
4.3.1.3. Medium Voltage Converter Application The effect of a multi-winding transformer on two medium power converters, i.e. the 3L-NPC VSC and 9L-SC2LHB VSC, is investigated. The steady state at 100% load with symmetrical
transformers, as calculated above, is assumed. Each 24-pulse transformer consists of two 12-pulse transformers. The model of one 12-pulse transformer is illustrated in Figure 4-16. To validate the obtained simulation results, MATLAB and Simplorer programs are used.
Table 4-6 The designing parameters for the 24-pulse transformer with Zdy connection
Figure 4-16 The model of a 12-pulse transformer
4.3.1.3.1. Three-Level Neutral Point Clamped Voltage Source Converter The first application example deals with the 24-pulse rectifier with serial diode-bridge-rectifier connections, which is used for the 3L-NPC VSC. The corresponding circuit is represented in Figure 4-17 and Figure 4-18 for the two aforementioned configurations.
The structure consists of the ac three-phase input source, four diode-bridge circuits, and two 12-pulse phase-shift transformers. The dc output is made of four 6-pulse rectifiers with a serial connection. The three-phase voltages of the rectifier input terminals are set to have a 15-degree phase difference. This connection allows supplying the four-diode rectifiers with 15-degree phase-shifted their phase voltage systems. This leads to a 24-pulse rectifier system.
L1 1.41[mH] R1 22.2[mΩ]
L2Y = L2D 130[µH] R2Y = R2D 2[µΩ]
Lm 85[H] Uk12Y = Uk12D 8[%]
Uk2YD 14[%] io 0.005[p.u.]
1 1j L Rω
mj Lω
1NU
1 1j L Rω
mj Lω
1NV
1 1j L Rω1NW
mj Lω 2 2D Dj L Rω
2 2Y Yj L Rω
2N DU
2N YU
2 2D Dj L Rω
2 2Y Yj L Rω
2N DV
2N YV
2 2D Dj L Rω
2 2Y Yj L Rω
2N DW
2N YW
MODELLING AND SIMULATION 89
Figure 4-17 24-Pulse-Diode-Rectifier with serial connections and Dzz configuration
Figure 4-18 24-Pulse-Diode-Rectifier with serial connections and Zdy configuration
4.3.1.3.1.1. Simulation Results Figure 4-19 to Figure 4-21 represent the simulation results assuming an ideal current source as load. As expected, the first dominant ac supply phase current harmonics are the 23rd and the 25th ones, according to Figure 4-19b. The first dominant primary and secondary current
-22.5°
-7.5°
7.5°
22.5°
POWER TRANSFORMERWITH ISOLATED SECONDARY WINDING RECTIFIER
UsA
isA
Ls Rs
UsB Ls Rs
UsC Ls Rs
idc
INPUT POWERTHREE-PHASE
AC SOURCE
-7.5°Ip1
Ip2
Is1
Is3
Is2
Is4
7.5°
Udc
Ip1
Is1
Is2
Is3
Is4
-22.5°
-7.5°
7.5°
22.5°
POWER TRANSFORMERWITH ISOLATED SECONDARY WINDING RECTIFIER
UsA
isA
Ls Rs
UsB Ls Rs
UsC Ls Rs
idc
INPUT POWERTHREE-PHASE
AC SOURCE
Ip2
Udc
90 MODELLING AND SIMULATION
harmonics are the 11th, 13th and 5th, 7th ones, according to Figure 4-19c and Figure 4-19e respectively. The harmonics analysis results confirm the proposed 24-pulse modelling.
Figure 4-19 Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b),
primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e, f) (see Figure 4-17)
0.04 0.045 0.05 0.055 0.06-500
0
500
i s,x
[A]
Time [sec.]
isAisBisC
0 10 20 30 40 50
100
101
102
103
Am
plitu
de i
sAHarmonics order
0.04 0.045 0.05 0.055 0.06
-200
-100
0
100
200
I p1,x
[A
]
Time [sec.]
Ip1UIp1VIp1W
0 10 20 30 40 50
100
101
102
Am
plitu
de I p
1U
Harmonics order
0.04 0.045 0.05 0.055 0.06-800
-600
-400
-200
0
200
400
600
800
I s1,x
Time [sec.]
Is1UIs1VIs
1W
0 10 20 30 40 5010
0
101
102
103
Am
plitu
de I s1
U
Harmonics order
(a) (b)
(c) (d)
(e) (f)
MODELLING AND SIMULATION 91
Figure 4-20 Primary and secondary winding currents of the 24-pulse transformer
Figure 4-21 DC link voltage and its harmonic spectrum (a, b), and dc link current and its
harmonic spectrum (c, d), idc = 710A, fC = 750Hz (see Figure 4-17)
0.04 0.045 0.05 0.055 0.06-200
-100
0
100
200
I px [
A]
Time [sec.]
Ip1Ip2
0.04 0.045 0.05 0.055 0.06
-500
0
500
I sx [
A]
Time [sec.]
Is1Is2Is3Is4
0.04 0.045 0.05 0.055 0.065950
6000
6050
6100
6150
6200
6250
6300
Udc
[V]
Time [sec.] 0 10 20 30 40 50
101
102
103
Am
plitu
de U
dc
Harmonics order
0.04 0.045 0.05 0.055 0.06
715
716
717
718
719
720
i dc [A
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de i d
c
Harmonics order
(a) (b)
(c) (d)
92 MODELLING AND SIMULATION
4.3.1.3.2. Nine-Level Series Connected H-Bridge Voltage Source Converter The second application example deals with the 24-pulse dc supply with independent diode-bridge-rectifier connections, which is used for the 9L-SC2LHB VSC. The corresponding circuits are represented in Figure 4-22 only for one motor phase. The dc supply is made of four separate 6-pulse transformers, each one leading to a 6-pulse rectifier system. The three-phase voltages of the rectifier input terminals are set to have a 15°-phase difference, which generates a 24-pulse rectifier system.
Figure 4-22 24-Pulse-Diode-Rectifier with independent connections: (a) Dzz configuration, and
(b) Zdy configuration
Ip1
Is1
Is2
Is3
Is4
-22.5°
-7.5°
7.5°
22.5°
POWER TRANSFORMERWITH ISOLATED SECONDARY WINDING RECTIFIER
UsA
isA
Ls Rs
UsB Ls Rs
UsC Ls Rs
INPUT POWERTHREE-PHASE
AC SOURCE
Ip2
idc1
idc2
idc3
idc4Udc,4
Udc,3
Udc,2
Udc,1
(a)
-22.5°
-7.5°
7.5°
22.5°
POWER TRANSFORMERWITH ISOLATED SECONDARY WINDING RECTIFIER
UsA
isA
Ls Rs
UsB Ls Rs
UsC Ls Rs
INPUT POWERTHREE-PHASE
AC SOURCE
-7.5°Ip1
Ip2
Is1
Is3
Is2
Is4
7.5°
idc1
idc2
idc3
idc4Udc,4
Udc,3
Udc,2
Udc,1
(b)
MODELLING AND SIMULATION 93
4.3.1.3.2.1. Simulation Results Figure 4-23 to Figure 4-26 represent the simulation results in the steady state at 100% load, which are the equivalent to that of the 3L-NPC VSC. As expected, the first dominant ac supply phase current harmonics are the 23rd and the 25th ones, according to Figure 4-23b. The harmonics analysis results confirm the proposed 24-pulse modelling. The first dominant primary and secondary current harmonics are the 11th, 13th and 5th, 7th ones, according to Figure 4-23d and Figure 4-23e respectively.
Figure 4-23 Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b),
primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e,f) (see Figure 4-18)
0.04 0.045 0.05 0.055 0.06-150
-100
-50
0
50
100
150
i s,x [
A]
Time [sec.]
isAisBisC
0 10 20 30 40 5010-1
100
101
102
Am
plitu
de i
sA
Harmonics order
0.04 0.045 0.05 0.055 0.06-80
-60
-40
-20
0
20
40
60
80
I p1,x
[A
]
Time [sec.]
Ip1UIp1VIp1W
0 10 20 30 40 5010-1
100
101
102
Am
plitu
de I
p1U
Harmonics order
0.04 0.045 0.05 0.055 0.06-600
-400
-200
0
200
400
600
I s1,x
[A]
Time [sec.]
Is1UIs1VIs1W
0 10 20 30 40 50
100
101
102
103
Am
plitu
de I
s1U
Harmonics order
(a) (b)
(c) (d)
(e) (f)
94 MODELLING AND SIMULATION
Figure 4-24 Primary and secondary winding currents of the 24-pulse transformer
Figure 4-25 DC link voltage and its harmonic spectrum, fC= 750Hz (see Figure 4-18)
Figure 4-26 DC link current and its harmonic spectrum, idc = 471A, fC = 750Hz (see Figure 4-18)
0.04 0.045 0.05 0.055 0.06-80
-60
-40
-20
0
20
40
60
80
I px [
A]
Time [sec.]
Ip1Ip2
0.04 0.045 0.05 0.055 0.06-600
-400
-200
0
200
400
600
I sx [
A]
Time [sec.]
Is1Is2Is3Is4
0.06 0.065 0.07 0.075 0.08471.5
471.6
471.7
471.8
471.9
472
i dc,x [A
]
Time [sec.]
idc1idc2idc3idc4
0 10 20 30 40 50
10-2
100
102
Am
plitu
de i
dc,x
Harmonics order
0.06 0.065 0.07 0.075 0.08650
700
750
800
850
900
Udc
,x [V]
Time [sec.]
Udc1Udc2Udc3Udc4
0 10 20 30 40 50
100
102
103
Am
plitu
de U
dc1
Harmonics order
5. DESIGN CRITERIA AND CONVERTER DATA
This chapter defines the design criteria and technical data of the typical available industrial medium voltage drives (the 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and 9L-SC2LHB VSC) which will be compared in detail in chapter 6.
5.1. Design Criteria The design process of a power converter depends on the topology and the converter specifications including line-to-line voltage Ull,rms,1, phase current Iph,rms,1, and the apparent converter output power SC, which have a critical influence on the overall characteristics, performance, and cost of any design.
5.1.1. Power Semiconductor Devices The selection of power semiconductors fundamentally determines the design and the performance as well as the investment and operating costs of power converters. IGBTs are usually used as power semiconductors in medium and high power applications [18], [78] due to their technical advantages.
When designing an IGBT/diode, important technical characteristics are:
UCE : Rated collector-emitter voltage.
IC,n / IF,n : Rated IGBT/Diode current.
URRM : Repetitive peak reverses voltage of diodes.
Tj,max : Maximum junction temperature range within the IGBT/Diode may be operated.
Rth,jc, Rth,ch : Thermal resistances of the IGBT/diode from junction to case and case to heat sink.
Th : Temperature of the heat sink.
Eon /Eoff : Turn-on / turn-off dissipation energy in the IGBT.
Erec : Recovery dissipation energy in the Diode.
Ucom@100FIT : The voltage Ucom@100FIT characterizes the device commutation voltage for a device reliability of 100FIT (where 1FIT corresponds to one failure in 109 operation hours) due to cosmic radiation. For a steady state operation, this voltage should be higher than the dc link voltage (Ucom@100FIT > Udc,n).
The installed switch power SS is a measureof the semiconductor cost and can be defined as
0 5S CE C ,n T RRM F ,n DS U I n . U I n= × × + × × × (5-1)
where nT and nD denote the number of semiconductors and diodes in the converter.
Considering that the diode area is typically only about 50% of that of the IGBTs in IGBT modules, the diodes are weighted with 50% compared to the IGBTs (equation 5-1), [29], [147].
96 DESIGN CRITERIA AND CONVERTER DATA
The relative installed switch power is calculated by normalizing the installed switch power of a certain converter topology to the installed switch power of the reference topology (e.g. the 3L-NPC VSC) [29].
3
100SSR
S , L NPC VSC
SSS −
= × (5-2)
This definition enables a comparison of the installed switch powers as a measure for the expense of semiconductors of the different converter topologies with respect to the 3L-NPC VSC.
The dimensioning of the semiconductor devices is based on the electrical and thermal data given in module specification datasheets. The switching frequency and output power of the MV converters are limited by the junction temperature Tj of the semiconductor devices. For a safe operation, the junction temperature must never exceed the maximum value Tj,max, whereby the average power losses in frequency ranges of 5Hz to 50Hz are considered (operating range). Therefore, the cooling of power semiconductors and thus the power dissipation in the semiconductors are criteria for the dimensioning of these devices. However, the operating range of fo < 5Hz, failure conditions, and dynamic procedures (e.g. overload, connection, and disconnection of the converter) are not examined in this thesis. Figure 5-1 depicts the suggested iterative approach to the power semiconductor design.
By using this chart, it is possible to determine the installed switch power, the semiconductor losses, and the necessary silicon area. To select the suitable device, an iterative MATLAB program is used, which allows to select the calculation of the required switch ratings. Essentially, it starts by providing a screen with different critical operation points related to the topology. The number of ideal parallel connections is selected so that the mostly stressed device never exceeds the maximum junction temperature Tj,max in all critical operating points (Table 5-1) of a four-quadrant operation [20], [25]. A maximum junction temperature greater than 125°C is an indication that the number of ideal parallel connections should be changed and more silicon area is necessary.
Furthermore, to evaluate the converter topologies for a variety of applications, four different categories are discussed and simulated in chapter 6. In a first step, a constant carrier frequency and a constant installed switch power SS are assumed. This approach allows a comparison between the maximum converter output power SC,max and the semiconductor utilization of the considered converter topologies. Figure 5-2 shows the applied calculation method.
In the second comparison, a constant installed switch power SS (which is a measure for the cost of semiconductors) as well as an equal output current and a constant converter output power SC are assumed to calculate the maximum carrier frequency of the considered converter topologies, as shown in Figure 5-3.
Table 5-1 Critical operating points for the determination of the power semiconductor current ratings (stationary thermal design) for all considered topologies [20], [25]
Figure 5-1 Iterative design approach to the power semiconductor design
0 99 j ,sp j j ,sp. T T T≤ ≤
Converter specificationsUll,rms,1, Iph,rms,1, SC
Calculation of the nominal dc link voltage
Udc,n = f (Ull,rms,1)
Calculation of the commutation voltage and the rated device voltage
(Ucom, UCE) = f (Udc,n)
Calculation of the power semiconductor losses and the junction
temperature in 4Q-operation (Ploss, Tj)
Adaption of the rated device current IC,n (IF,n ) and thermal resistance Rth
by cf to provide the condition
1
No
Yes
Calculation of the installed switch power SS for all considered topologies
Adaption of the current factor cf to provide the constant installed switch
power SS for all considered topologies
98 DESIGN CRITERIA AND CONVERTER DATA
Figure 5-2 Iterative design approach to calculate the maximum converter output power SC,max
and the semiconductor utilization (Tj = Tj,max, SS = const., fC = const.)
Figure 5-3 Iterative design approach to calculate the maximum carrier frequency
(Tj = Tj,max, SS = const., SC = const.)
The third condition for a converter comparison is the constant installed switch power SS and a constant frequency of the first harmonic carrier band f1Cb, according to Figure 5-4. This approach allows a comparison between the converter output power and losses of the considered converter topologies. If the first harmonic carrier band occurs at around the same frequency, the design of an output filter with about the same size and weight is enabled.
The constant converter power SC and a constant converter efficiency η are assumed for a fourth condition to calculate the carrier frequency, achieving a maximum junction temperature of Tj,max in one worst case operating point of the converter (see Figure 5-5). The chosen efficiency is typical for state-of-the-art medium voltage converters.
0 99 j ,sp j j ,sp. T T T≤ ≤
Iph = constant
Variation of the carrier frequency fC to provide the condition
1
Results
No
Yes C ,max lossf ,P ,η
0 99 j ,sp j j ,sp. T T T≤ ≤
fC = constant
Variation of the output converter current Iph
1
Results
No
Yes ph,max C ,max lossI ,S ,P ,η
DESIGN CRITERIA AND CONVERTER DATA 99
Figure 5-4 Iterative design approach to calculate the converter output power and losses
(Tj = Tj,max, SS = const., f1Cb = const.)
Figure 5-5 Iterative design approach to calculate the maximum carrier frequency
(Tj = Tj,max, SC = const., η = ηref ≈ const.)
0 99 j ,sp j j ,sp. T T T≤ ≤
η = constant
Adaption of the rated device current IC,n (IF,n ) and thermal resistance Rth to provide the condition
1
Results
No
Yes lossP , ,...η
refη η≤
Variation of the carrier frequency fC to provide the condition
0 99 j ,sp j j ,sp. T T T≤ ≤
f1Cb = constant
Variation of the output converter current Iph
1
Results
No
Yes ph,max C ,max lossI ,S ,P ,η
Calculation of the switching frequency fC for all topologies
100 DESIGN CRITERIA AND CONVERTER DATA
5.1.2. DC Link Capacitor Different criteria are given in the literature for the dimensioning of the dc link capacitor [10], [65], [77], [138], and [141]. Design criteria like dc link voltage ripples and dc link capacitor storage energy play important roles in sizing the dc link capacitor and they are therefore examined in this thesis in order to choose the most suitable amount and size of dc link capacitors.
5.1.2.1. DC Link Voltage Ripples The primary function of the dc link capacitor is to filter the dc link voltage and to provide a stable dc voltage link for the inverter section. The impermissible dc link voltage ripples may have unfavourable effects on the operation of the drive. They increase the current harmonics and the electromagnetic interference (EMI) of the drive and negatively affect the electric machine. Other possible consequences are an increase of electric losses, higher supply current harmonics, an excessive rise of motor temperature, appearance of torque pulsations on the machine side, noise problems, and a higher risk of semiconductor failure. A solution to these problems is an appropriate design of the dc link capacitor. For this purpose, this section first presents an equation to determine the minimum size of the dc link capacitor for the NPC and SCHB topologies as a function of the voltage ripple ∆UC, which is derived in [140], [144].
212
Cmin,NPC
CC dc rec
PCUU U f
=∆⎛ ⎞∆ − ⋅⎜ ⎟
⎝ ⎠
(5-3)
21
412
C amin,SCHB
CC dc rec
P mC sin arccosUU U f
π⎡ ⎤⎛ ⎞⎛ ⎞= −⎢ ⎥⎜ ⎟⎜ ⎟∆⎛ ⎞ ⎝ ⎠⎝ ⎠⎣ ⎦∆ − ⋅⎜ ⎟⎝ ⎠
(5-4)
where PC denotes the converter output active power in watts, ma is the modulation index and frec is the rectifier output frequency in hertz.
5.1.2.2. DC Link Capacitor Stored Energy Stored energy is a measure to compare the different converter topologies with each other and/or to compare the different applications of a topology with each other. This size is also a measure for ride-through capability. Power disturbance ride-through capability can be defined as the ability of a drive to maintain the motor output power with a power line disturbance or drop voltage at the drive input. If there is an input power disturbance, the dc link voltage will drop and the drive will stop the motor after a short time. During a power ride-through capability, the input power is removed and the stored energy in the dc link capacitor bank is the only source of power available to run the motor. Then, the stored energy per kVA is a measure of the ride-through capability as well as a measure of the cost and volume of the dc link capacitor. The equation for the stored energy in a dc link capacitor is
212C dcE C U= × × (5-5)
It can be observed that the stored energy in a drive is directly proportional to the dc link capacitance and proportional to the square of the dc link voltage. However, not the entire stored energy is available for the drive to provide output power to the motor.
If the ride-through capability time is under one second, it is very likely that the energy requirement is supplied by the internal dc link capacitor. If, however, the required energy is only
DESIGN CRITERIA AND CONVERTER DATA 101
slightly more than the stored energy of the dc link capacitor, an increase in the dc link capacitor and a recalculation of the available energy should be considered.
Figure 5-6 illustrates the relations between the dc link voltage ripple and the stored energy for the 3L-NPC VSC as a function of the dc link capacitance, using equations (5-3) and (5-5).
An increase of the dc link capacitance increases the stored energy and decreases the dc link voltage ripple. It is to remark that the application of the dc link capacitance C = 2.77mF enables a reduction of the dc link voltage ripple by 51% at twice the stored energy, compared to the use of the dc link capacitance C = 1.39mF at a stored energy of 6J/kVA.
Figure 5-6 The dc link voltage ripple ∆UC and the dc link stored energy EC as functions of the
dc link capacitance for the 3L-NPC VSC (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos ϕ = 0.9, Udc = 6118V)
5.1.2.3. Design of the Flying Capacitors Assuming sinusoidal converter output voltages and currents, equation (5-5) can be used as an approximation to determine the capacitance of the flying capacitors of a 3L-FLC VSC and a 4L-FLC VSC
1ph,rms ,
C C C
IC
n U f=
×∆ × (5-6)
where 1ph,rms ,I denotes the amplitude of the phase current, nC is the number of series connected flying capacitor cells, fC is the carrier frequency, and ∆UC denotes the maximum voltage ripple across the flying capacitors.
“For the design being realized the maximum capacitor voltage ripple ∆UC,max was specified to 15% of the rated flying capacitor voltage of the 3L-FLC VSC for both flying capacitor converters (∆UC,max = 0.15×Udc,n/2).” [29] To verify the approximation according to (5-5), the voltage ripple ∆UC and current iC,rms of the flying capacitors of a 3L-FLC VSC and a 4L-FLC VSC are studied in section 6.1.4.
2 4 6 8 10 12 14
5
10
15
20
C =
1.39
[mF]
C =
2.77
[mF]
EC [J/kVA]
∆UC
[%]
102 DESIGN CRITERIA AND CONVERTER DATA
5.2. Definition of the Converter Data Table 5-2 depicts the characteristic converter data for the output phase current Iph,rms,1 = 600A, which is used for the comparison of the investigated converter topologies in chapter 6. Today, the line-to-line voltages of 2.3kV, 3.3kV, and 4.16kV are usually used for MVDs. However, due to the development of 6kV-7.2kV MVDs in the last years, rated voltages of 6.2kV and 6.9kV are also selected.
Table 5-2 Converter data (Output phase current Iph,rms,1 = 600A)
5.2.1. Power Semiconductor Devices
Table 5-3 summarizes the power semiconductor devices in the voltage classes of 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV from several manufacturers, which are used in this thesis.
Table 5-3 Power semiconductor devices [156], [158], [160]
Converter line-to-line voltage Ull,rms,1 2.3kV, 3.3kV, 4.16kV, 6.2kV, and 6.9kV
Apparent converter output power Sc 2.4MVA, 3.4MVA, 4.3MVA, 6.4MVA, and 7.2MVA Nominal dc link voltage Udc,n 3383V, 4853V, 6118V, 9119V, and 10148V Phase current Iph,rms,1 600A Converter output frequency fo 50Hz Converter efficiency ≈ 99% Output voltage THD according to IEEE 519-1999 5%
Modulation Natural sampled sine-triangle modulation with 1/6 added third harmonics
Carrier frequency fC 450Hz – 1050Hz Maximum junction temperature Tj,max (IGBT, diode) 125°C
5.2.2. Switching Frequency The considered converter topologies are modulated by a sine-triangle modulation with an addition of 1/6th of third harmonics. To evaluate the converter topologies for a variety of applications, carrier frequencies of fC = 450Hz ... 1050Hz are assumed for all investigated converter topologies. This range is typical for available industrial medium voltage drives.
5.2.3. DC Link Voltage The minimum dc link voltage Udc,min to achieve a certain line-to-line output voltage by using a sine-triangle modulation with 1/6 added third harmonics for all topologies is calculated by
12dc ,min ll ,rms ,U U= × (5-6)
To determine the nominal dc link voltage of the converter Udc,n, a control voltage reserve of 4% is assumed, which is needed for dynamic processes and filter voltage drops.
1 04dc ,n dc ,minU . U= × (5-7)
Due to the circuit structure of the SC2LHB VSCs, the minimum dc link voltage of one H-bridge Udc,HB depends on the number of series connected H-bridges p. It is determined by equation (3-30) and can be rewritten as
2dc ,n
dc ,HB
UU
p= (5-8)
To evaluate the harmonic spectrum of the line-to-line output voltage, the total harmonic distortion (THD) and the weighted total harmonic distortion (WTHD) are being considered (based on equation 5-9).
( )2
2
22
1 1
ll ,hll ,h
hh
ll , ll ,
UU
hTHD , WTHD
U U
∞∞
==
⎛ ⎞⎜ ⎟⎝ ⎠= =
∑∑ (5-9)
where h denotes the order of harmonics.
The weighted total harmonic distortion is a measure of the harmonic content for the output current and the harmonic losses in the load.
5.2.4. Rectifier Depending on the inverter configuration, two types of diode rectifiers are used: (1) series-type, where the dc sides of the standard six-pulse diode rectifiers are connected in series which uses for the 3L-NPC VSC and (2) separate-type, where each dc side is connected directly which uses for the 9L-SCHB VSC. The block diagrams of a 24-pulse-diode-bridge configuration for both applications are depicted in Figure 5-7.
5.2.5. General Data for the Selective Medium Voltage Converters Figure 5-8 illustrates the selected medium voltage drives in the 2.4MVA to 7.2MVA range with voltage ratings from 2.3KV to 6.9KV at a phase current rating of 600A. The technical data of the selected medium voltage topologies (e.g. the 2L-VSC, 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and SC2LHB VSCs), which are analyzed in this thesis, are also summarized in Table 5-4. State-of-the-art 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs are examined. The converter ratings were chosen so that they are comparable with the ratings of commercially
104 DESIGN CRITERIA AND CONVERTER DATA
available topologies.
It is interesting to note that the same technical data are utilizable for both 3L-VSCs due to the same voltage utilization of the semiconductors. However, the required current rating to achieve a certain output current is different because of the different circuit structures and modulation schemes. In SC2LHB VSCs, the number of series connected H-bridges differs according to the required line-to-line output voltage and if 1.7kV IGBT moduls are applied. Today, the use of the 1.7kV IGBT moduls is state-of-the-art for all considered output voltage classes of the SC2LHB VSCs.
Figure 5-7 24-pulse diode rectifier configurations: (a) series configuration uses for the 3L-NPC
VSC, (b) separate configuration uses for the9L-SCHB VSC
Figure 5-8 Voltage and power ranges of the selective medium voltage drives (Iph,rms,1 = 600A),
Number of cells per phase/Number of levels per phase4/9 5/112/5 6/13
1.7kV IGBT
6.9kV2.3kV 3.3kV 4.16kV 6.6kV
Voltage range
2.4MVA 6.4MVA 7.2MVA3.4MVA 4.3MVAPower range
2×3.3kV IGBT
(a) Series configuration (b) Seperate configuration
7.5°
-22.5°
-7.5°
22.5°-7.5°
7.5°
7.5°
-22.5°
-7.5°
22.5°-7.5°
7.5°
DESIGN CRITERIA AND CONVERTER DATA 105
Table 5-4 The converter specifications for medium voltage converters
Converter specifications for the 2L-VSC
Converter line-to-line voltage Ull,rms,1 2.3kV 3.3kV
Apparent converter output power Sc 2.4MVA 3.4MVA Nominal dc link voltage Udc,n 3383V 4853V Commutation voltage Ucom = Udc,n 3383V 4853V Rated device voltage UCE,n 6.5kV IGBT 2×4.5kV IGBT Ucom@100FIT 3600V 2250V Ucom/Ucom@100FIT 0.94 1.08
Converter specifications for the 3L-VSCs
Converter line-to-line voltage Ull,rms,1 2.3kV 3.3kV 4.16kV
Apparent converter output power Sc 2.4MVA 3.4MVA 4.3MVA Nominal dc link voltage Udc,n 3383V 4853V 6118V Commutation voltage Ucom = Udc,n/2 1691.5V 2426.5V 3059V
Converter specifications for the SC2LHB VSC Converter line-to-line voltage Ull,rms,1 2.3kV 3.3kV 4.16kV 6.2kV 6.9kV Apparent converter output power Sc 2.4MVA 3.4MVA 4.3MVA 6.4MVA 7.2MVANominal dc link voltage Udc,n 3383V 4853V 6118V 9119V 10148V Number of series connected H-bridges p 2 3 4 5 6 Dc link voltage of one H-bridge Udc,HB 846V 809V 765V 912V 846V Commutation voltage Ucom = Udc,HB 846V 809V 765V 912V 846V Number of phase voltage level (2p + 1) 5 7 9 11 13 Number of line-to-line voltage level (4p + 1) 9 13 17 21 25 Rated device voltage UCE,n 1.7kV IGBT Ucom@100FIT 900V Ucom/Ucom@100FIT 0.94 0.9 0.85 1.01 0.94
6. CONVERTER COMPARISON
This chapter compares 2.3kV, 3.3kV, 4.16kV, and 6kV medium voltage converters on the basis of the 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC and 5L-, 7L-, 9L-, and 11L-SC2LHB VSCs topologies applying state-of-the-art 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs. The design of semiconductors and passive components, the semiconductor loss distribution, converter losses, the installed switch power, and the harmonic spectrum will be compared in detail.
6.1. Comparison of Power Semiconductor Utilization and Loss Distribution Table 6-1 summarizes the design of the power semiconductors for the two carrier frequencies of fC = 450Hz and fC = 1000Hz at a phase current of Iph,rms,1 = 600A and a maximum junction temperature of Tj,max = 125°C for converter voltages of 2.3kV, 3.3kV, and 4.16kV in all investigated topologies. The calculated ideal rated IGBT/diode currents IC,n/IF,n (Figure 6-1) guarantee that the junction temperature of the mostly stressed IGBT or diode reaches a value of Tj,max = 125°C in one worst case operating point of a four-quadrant operation [20], [25].
To evaluate the converter topologies for a variety of applications, four different comparison cases are discussed in this section.
6.1.1. Comparison at Constant Installed Switch Power and Constant Carrier Frequency In a first step, a constant carrier frequency (fC = 450Hz / 1000Hz) is assumed for all considered converter topologies. The installed switch power SS of the 3L-, 4L-FLC VSCs, and SC2LHB VSCs are equal to that of the 3L-NPC VSC, achieving an output current of 600A in the corresponding output voltage class. This approach allows a comparison of the maximum converter output power SC,max and the semiconductor utilization of the considered converter topologies (Table 6-2).
For line-to-line output voltages of 2.3kV, 3.3kV, and 4.16kV, the SC2LHB VSCs enable a maximum converter output power SC,max, which is increased by 12.3%, 8.5%, and 36% in comparison to the corresponding 3L-NPC VSCs (Table 6-2 at fC = 450Hz).
The total converter losses, efficiencies, the loss distribution, and the harmonic spectrum of the investigated converter topologies are shown in Figure 6-1 to Figure 6-3, where the installed switch power and the carrier frequency (fC = 450Hz) are constant.
Figure 6-1 depicts the total converter losses (on the left) and efficiencies (on the right) as a function of the phase current in the three investigated output voltage classes. These figures show that the 3L-NPC VSCs feature less losses and therefore superior efficiencies, compared to other topologies in the three investigated output voltage classes. The losses of the 5L-SC2LHB VSC are smaller in the entire current range than those of the 3L- and 4L-FLC VSCs, assuming a line-to-line voltage of 2.3kV. The 7L- and 9L-SC2LHB VSCs feature fewer losses up to a phase current 400A for a line-to-line voltage of 3.3kV and 600A for a line-to-line voltage of 4.16kV, compared to the corresponding 3L- and 4L-FLC VSCs.
Figure 6-2 shows the loss distribution and the switch utilization of the considered converter topologies if a constant phase current of Iph,rms,1 = 600A and a constant carrier frequency of fC =
108 CONVERTER COMPARISON
450Hz are assumed. It is interesting to note that the converter losses (in the left part of Figure 6-2) of the 5L-SC2LHB VSC, 4L-FLC VSC, and 3L-FLC VSC are increased by 2.6%, 46.8%, and 12.8%, compared to the 3L-NPC VSC (Ull,rms,1 = 2.3kV, SC = 2.39MVA). Furthermore, the 7L-SC2LHB VSC, 4L-FLC VSC, and 3L-FLC VSC generate 61.5%, 77.7%, and 41.36% more semiconductor losses, compared to the 3L-NPC VSC (SC = 3.43MVA), if a line-to-line output voltage of 3.3kV is applied. For a line-to-line output voltage of 4.16kV the converter losses of the 9L-SC2LHB VSC, 4L-, and 3L-FLC VSCs produce 18.9%, 19.8%, and 42.4% more semiconductor losses, compared to the 3L-NPC VSC (SC = 4.32MVA).
Table 6-1 Power semiconductor design for Iph,rms,1 = 600A, fC = 450Hz / 1000Hz
Converter line-to-line voltage Ull,rms,1 = 2.3kV Dc link voltage Udc,n 3382.8V Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
Figure 6-1 Converter semiconductor losses and efficiencies as functions of the phase current
for the investigated output voltage classes (fC = 450Hz, ma = 1.15, cosϕ = 0.9): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
The switching losses of the 3L-FLC VSC are higher than that of the 3L-NPC VSC in the three considered output voltage classes (by 121% for 2.3kV, 127% for 3.3kV, and 115% for 4.16kV). Furthermore, the switching losses of the 4L-FLC VSC are increased by 145.6% (for 2.3kV), 58.6% (for 3.3kV), and 65.7% (for 4.16kV), compared to the corresponding 3L-NPC VSCs. In
200 400 600 800 10000
10
20
30
40
50
60
Phase current [A]
Con
verte
r sem
icon
duct
or lo
sses
[kW
]
3L-NPC3L-FLC4L-FLC5L-SC2LHB
200 400 600 800 100098.5
99
99.5
100
Phase current [A]
Effic
ienc
y [%
]
3L-NPC3L-FLC4L-FLC5L-SC2LHB
(a) Ull,rms,1 = 2.3kV
200 400 600 800 10000
10
20
30
40
50
60
Phase current [A]
Con
verte
r sem
icon
duct
or lo
sses
[kW
]
3L-NPC3L-FLC4L-FLC7L-SC2LHB
200 400 600 800 100098.5
99
99.5
100
Phase current [A]
Effic
ienc
y [%
]
3L-NPC3L-FLC4L-FLC7L-SC2LHB
(b) Ull,rms,1 = 3.3kV
200 400 600 800 10000
10
20
30
40
50
60
70
80
Phase current [A]
Con
verte
r sem
icon
duct
or lo
sses
[kW
]
3L-NPC3L-FLC4L-FLC9L-SC2LHB
200 400 600 800 100098.5
99
99.5
100
Phase current [A]
Effic
ienc
y [%
]
3L-NPC3L-FLC4L-FLC9L-SC2LHB
(c) Ull,rms,1 = 4.16kV
CONVERTER COMPARISON 111
contrast, the switching losses of the 5L-, 7L-, and 9L-SC2LHB VSC topologies are significantly lower than that of the 3L-NPC VSCs in all considered output voltage classes (by 10% for 2.3kV, 38% for 3.3kV, and 56% for 4.16kV), since the 1.7kV IGBTs generate distinctly less switching losses than the 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. The conduction losses of the 4L-FLC VSC occurring at line-to-line output voltages of 2.3kV and
Figure 6-2 Converter semiconductor loss distribution at constant carrier frequency
3.3kV are increased by 27% and 88% while decreased by 11.7% for 4.16kV, compared to the corresponding 3L-NPC VSCs.
The right part of Figure 6-2 shows that the SC2LHB VSCs and the FLC VSCs feature higher converter switch utilization than the 3L-NPC VSC, as a reference in the three investigated output voltage classes, while the converter switch utilization of the 4L-FLC VSC is decreased by 6.5% if a line-to-line output voltage of 2.3kV is applied.
Figure 6-3 illustrates that the first carrier band of the line-to-line output voltage of the 3L-NPC VSC occurs around the carrier frequency of fC = 450Hz. In contrast, the first carrier band of the line-to-line output voltage of the 3L-FLC VSC, 4L-FLC VSC, 5L-, 7L-, and 9L-SC2LHB VSC is centred around two, three, four, six, and eight times the carrier frequency. Hence, an output filter of the SC2LHB VSCs could be smaller than the corresponding filters of other topologies.
The THD decreases when the number of levels increases. The WTHD of the 9L-SC2LHB VSC is clearly lower than that of other topologies due to the nine-level characteristic of the output voltage. Assuming a constant carrier frequency (fC = 450Hz), the WTHD of the 3L-NPC VSC (1.49%) is almost three, three, five, and fifteen times larger than that of the 4L-FLC VSC, 5L-SC2LHB VSC, 7L-SC2LHB VSC, and 9L-SC2LHB VSC respectively (Table 6-2). It is important to note that the above-mentioned differences of the output voltage THD and WTHD are primarily caused by the circuit configurations.
Figure 6-3 Harmonic spectrum of line-to-line output voltage at constant carrier frequency
6.1.2. Comparison of Maximum Carrier Frequency at Constant Installed Switch Power and Constant Apparent Converter Output Power
In the second step, a constant installed switch power SS (which is a measure for the expense of semiconductors) as well as an equal output current (Iph,rms,1 = 600A) and constant converter output power SC are assumed (Table 6-3) to calculate the maximum carrier frequency of the considered converter topologies.
0 1 2 3 410
-2
10-1
100
3L-NPC
0 1 2 3 410
-2
10-1
100
3L-FLC
Nor
mal
ized
line
-to-li
ne v
olta
ge
0 1 2 3 410
-2
10-1
100
4L-FLC
Frequency [kHz]
0 1 2 3 410
-2
10-1
100
5L-SC2LHB
0 1 2 3 410
-2
10-1
100
7L-SC2LHB
Nor
mal
ized
line
-to-li
ne v
olta
ge
0 1 2 3 410
-2
10-1
100
9L-SC2LHB
Frequency [kHz]
CONVERTER COMPARISON 113
Table 6-3 Maximum carrier frequency for constant apparent converter output power and constant installed switch power (Iph,rms,1 = 600A, ma = 1.15, cosϕ = 0.9)
Converter line-to-line voltage Ull,rms,1 = 2.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB Device part number FZ800R33KF2 FZ800R33KF2 FZ1000R25KF1 FZ600R17KE3 Carrier frequency fC [Hz] 450 1000 450 1000 450 1000 450 1000 Installed switch power SS [MVA] 41.91 50.06 41.91 50.06 41.91 50.06 41.91 50.06 Rated IGBT current IC,n (IF,n) [A] 604.8 722.4 705.5 842.8 620.8 845.8 684.8 818 Phase current Iph,rms,1 [A] 600 600 600 600 600 600 600 600 Maximum apparent converter output power SC,max [MVA] 2.39 2.39 2.39 2.39 2.39 2.39 2.39 2.39
Maximum carrier frequency fC,max [Hz], @ Tj,max = 125°C, Iph,rms,1 = 600A
450 1000 880 1410 250 1240 1585 3050
Frequency of the first harmonics carrier band f1Cb [Hz] 450 1000 1760 2820 750 3720 6340 12200
The installed switch powers of all topologies are equal to those of the 3L-NPC VSC (Table 6-2) including NPC diodes. According to section 6.1.1, the maximum switching frequency results from the losses and junction temperatures of the mostly stressed devices (Tj,max = 125°C) at critical operating points.
Table 6-3 shows that the SC2LHB VSCs enables a higher maximum carrier frequency than the other investigated topologies. Figure 6-4 depicts the total converter losses (on the left) and efficiencies (on the right) as a function of the carrier frequency in the three investigated output voltage classes.
These figures demonstrate that the 5L-, 7L-, and 9L-SC2LHB VSC feature less losses and therefore high efficiencies, compared to the 3L-NPC VSCs, for a carrier frequency beyond 1000Hz, 2290Hz, and 790Hz respectively. Figure 6-5 depicts the power loss distribution and the maximum possible carrier frequencies for a constant apparent converter output power in the three investigated output voltage classes. Assuming a nominal phase current of Iph,rms,1 = 600A, the converter losses of the 5L-, 7L-, and 9L-SC2LHB VSC are increased by 42%, 105%, and 126% at the maximum carrier frequency in comparison to that of the 3L-NPC VSC. It is obvious that the 9L-SC2LHB VSC has the maximum converter losses at the maximum possible carrier frequencies and a line-to-line output voltage 4.16kV, compared to the other topologies. The switching and conduction losses of the 5L-, 7L-, and 9L-SC2LHB VSC are higher than that of the corresponding 3L-NPC VSCs (by 227% and 5% for 2.3kV, 83% and 117% for 3.3kV, and 207% and 70% for 4.16kV).
It is interesting to note that the 5L-, 7L-, and 9L-SC2LHB VSC clearly realize the maximum carrier frequencies in the three investigated output voltage classes.
The harmonic spectra of the line-to-line output voltage of the considered converters are shown in Figure 6-6 to Figure 6-8. The maximum carrier frequencies of the 3L-FLC VSCs are increased by factors of 1.95 (880Hz for 2.3kV), 1.4 (635Hz for 3.3kV), and 1.32 (595Hz for 4.16kV), compared to those of the 3L-NPC VSCs (fC,max = 450Hz). On the other hand, the maximum carrier frequency of the 4L-FLC VSC are increased by factors of 1.75 (790Hz for 3.3kV) and 1.88 (850Hz for 4.16kV), compared to those of the 3L-NPC VSCs (fC,max = 450Hz), whereas it is decreased by factors of 0.45 (250Hz for 2.3kV) (Table 6-3). Furthermore, the maximum carrier frequencies of the 5L-SC2LHB VSC (fC,max = 1585Hz), 7L-SC2LHB VSC (fC,max = 1300Hz), and 9L-SC2LHB VSC (fC,max = 3450Hz) are increased by factors of 3.5, 2.88, and 7.8, compared to those of the 3L-NPC VSCs (Table 6-3).
The first carrier band of the line-to-line voltage of the 4L-FLC VSC occurs around three times (f1Cb = 3fC) the carrier frequencies (750Hz for 2.3kV, 2370Hz for 3.3kV, and 2550Hz for 4.16kV). The first carrier band of the line-to-line voltage of the 5L-, 7L-, and 9L-SC2LHB VSCs occur around 6.34kHz, 7.8kHz, and 27.6kHz respectively, whereas the first carrier band generated by the 3L-NPC VSC occurs around the carrier frequency fC = 450Hz (Figure 6-8). Thus, for the three considered output voltage classes, the SC2LHB VSCs enable substantially reduced sine output filters, compared to those of the 3L-NPC VSCs and both flying capacitor topologies.
Comparing the WTHD at the maximum possible carrier frequency, the 9L-SC2LHB VSC features the minimum value of 0.02% since the harmonics of the first carrier band (f1Cb = 27.8kHz) are strongly damped. The WTHD of the 5L-SC2LHB VSC (0.12%) and the 7L-SC2LHB VSC (0.078%) are about 95% and 92% smaller than that of the 3L-NPC VSC (1.49%) since the first harmonics of the 5L-SC2LHB VSC and the 7L-SC2LHB VSC occur at four (f1Cb = 4fC) and six (f1Cb = 6fC) times the carrier frequency, compared to those of the 3L-NPC VSC (f1Cb = fC).
CONVERTER COMPARISON 115
Figure 6-4 Converter semiconductor losses and efficiencies as functions of the carrier
frequency for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC = 450Hz, Iph,rms,1 = 600A, ma = 1.15, cosϕ = 0.9) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
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3L-NPC3L-FLC4L-FLC7L-SC2LHB
(b) Ull,rms,1 = 3.3kV
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3L-NPC3L-FLC4L-FLC9L-SC2LHB
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3L-NPC3L-FLC4L-FLC9L-SC2LHB
(c) Ull,rms,1 = 4.16kV
116 CONVERTER COMPARISON
Figure 6-5 Converter semiconductor loss distribution at maximum carrier frequency
(fo = 50Hz, ma = 1.15, cosϕ = 0.9, Iph,rms,1 = 600A, fC = 450Hz), (fC,3L-NPC = 450Hz, fC,3L-
6.1.3. Comparison of Converter Power and Loss Distribution at Constant Installed Switch Power and Constant Frequency of the First Carrier Band
The conditions for the third comparison are constant installed switch power SS and constant frequency of the first harmonic carrier band f1Cb. To place the first harmonic carrier band at the frequency occurring in the 3L-NPC VSC (f1Cb = fC = 450Hz), the carrier frequencies of the different topologies have to be reduced (Table 6-4). This approach allows a comparison of the converter output power and the losses of the considered converter topologies. If the first harmonic carrier band occurs around the same frequency, the design of an output filter of about the same size and cost range is enabled.
The maximum apparent converter output powers SC,max of the 5L-, 7L-, and 9L-SC2LHB VSCs are increased by 15%, 10.5%, and 37%, in comparison to the 3L-NPC VSC (Table 6-4).
Figure 6-9 shows the total converter losses and efficiencies as a function of the phase current and Figure 6-10 illustrates the power loss distribution and the converter switch utilization of the investigated topologies whereas the installed switch power and the frequency of the first harmonics carrier band are constant (f1Cb = fC = 450Hz). The losses of the 5L SC2LHB VSC are smaller in the entire current range (left part of Figure 6-9) and therefore its efficiency is higher (right part of Figure 6-9), compared to that of the corresponding 3L-NPC VSC, assuming a line-to-line output voltage of 2.3kV. In contrast, the 7L- and 9L SC2LHB VSCs feature fewer losses at a phase current of up to 213A and 518A than the corresponding 3L-NPC VSC. The semiconductor losses of the 4L-FLC VSC are larger in the entire current range for a line-to-line output voltage of 2.3kV, compared to those of the corresponding 3L-NPC VSC.
Assuming a nominal phase current of Iph,rms,1 = 600A, the 5L-, 7L-, and 9L-SC2LHB VSCs feature 8.4% lower, 44.2%, and 3.3% higher losses, compared to the corresponding 3L-NPC VSCs (Figure 6-10).
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CONVERTER COMPARISON 119
Table 6-4 Maximum phase current and apparent converter output power for the constant carrier frequency of the first carrier band and installed switch power (Iph,rms,1 = 600A, f1Cb = 450Hz / 1000Hz, ma = 1.15, cosϕ = 0.9)
Converter line-to-line voltage Ull,rms,1 = 2.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB Device part number FZ800R33KF2 FZ800R33KF2 FZ1000R25KF1 FZ600R17KE3 Frequency of the first harmonics carrier band f1Cb [Hz] 450 1000 450 1000 450 1000 450 1000
Installed switch power SS [MVA] 41.91 50.06 41.91 50.06 41.91 50.06 41.91 50.06 Rated IGBT current IC,n (IF,n) [A] 604.8 722.4 705.5 842.8 620.8 845.8 684.8 818 Carrier frequency fC [Hz] 450 1000 225 500 150 333.3 112.5 250 Maximum phase current Iph,max [A] @ Tj,max = 125°C 600 600 750 816 621 804 689 806
Maximum apparent converter output power SC,max [MVA] 2.39 2.39 2.98 3.25 2.47 3.2 2.75 3.21
Converter line-to-line voltage Ull,rms,1 = 3.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB Device part number CM600HB-90H CM600HB-90H FZ800R33KF2 FZ600R17KE3 Frequency of the first harmonics carrier band f1Cb [Hz] 450 1000 450 1000 450 1000 450 1000
Installed switch power SS [MVA] 60.67 95.88 60.67 95.88 60.67 95.88 60.67 95.88 Rated IGBT current IC,n (IF,n) [A] 642 1014.6 749 1183.7 681 1076 660.8 1044 Carrier frequency fC [Hz] 450 1000 225 500 150 333.3 75 166.7 Maximum phase current Iph,max [A] @ Tj,max = 125°C 600 600 717 1005 715 1086 664 1046
Maximum apparent converter output power SC,max [MVA] 3.43 3.43 4.09 5.74 4.08 6.2 3.79 5.98
Converter line-to-line voltage Ull,rms,1 = 4.16kV Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB Device part number FZ600R65KF1 FZ600R65KF1 CM600HB-90H FZ600R17KE3 Frequency of the first harmonics carrier band f1Cb [Hz] 450 1000 450 1000 450 1000 450 1000
Installed switch power SS [MVA] 101.1 157.2 101.1 157.2 101.1 157.2 101.1 157.2 Rated IGBT current IC,n (IF,n) [A] 740.4 1152 863.7 1344 832 1294 825.8 1285 Carrier frequency fC [Hz] 450 1000 225 500 150 333.3 56.25 125 Maximum phase current Iph,max [A] @ Tj,max = 125°C 600 600 885 1020 801 1188 821 1316
Maximum apparent converter output power SC,max [MVA] 4.32 4.32 6.37 7.35 5.77 8.56 5.92 9.48
The switching losses of the 5L-, 7L-, and 9L-SC2LHB VSCs are significantly lower than those of the 3L-NPC VSC (76% for 2.3kV, 88% for 3.3kV, and 94% for 4.16kV), since the 1.7kV IGBTs generate distinctly less switching losses than the 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. On the other hand, the conduction losses of the 5L-, 7L-, and 9L-SC2LHB VSCs are increased by 5% for 2.3kV, 118% for 3.3kV, and 70% for 4.16kV, compared to the corresponding 3L-NPC VSC topologies.
For a line-to-line output voltage of 2.3kV, the 4L-FLC VSC features the highest losses and the lowest converter output power, whereas the 7L- and 9L-SC2LHB VSCs have the maximum value for line-to-line output voltages of 3.3kV and 4.16kV respectively.
The 3L-FLC VSC enables the maximum converter switch utilization, compared to that of the corresponding 3L-NPC VSCs in the three investigated output voltage classes, as shown in the right part of Figure 6-10.
Furthermore, both three-level topologies provide the poorest THD and WTHD (Table 6-4). Both the THD and the WTHD of the 9L-SC2LHB VSC are clearly the smallest, since the distortion of the output voltage is at a minimum due to the applied nine levels.
The harmonic spectra of the converters are shown in Figure 6-11. The first carrier band of all investigated topologies occurs at about the first harmonic carrier band f1Cb.
Figure 6-11 Harmonic spectrum of line-to-line voltage at constant frequency of the first carrier
Figure 6-12 shows the junction temperatures of IGBTs and diodes of one phase leg of the investigated topologies. It is apparent that all IGBTs and diodes reach their maximum junction temperature at the critical operating point 2, see Table 5-1.
Figure 6-12a demonstrates that the junction temperatures of a 3L-NPC VSC are not equally distributed, unlike in the other topologies (Figure 6-12b through Figure 6-12d). This non-
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CONVERTER COMPARISON 123
equality leads to the maximum junction temperature to the outer IGBTs (T2 and 1Τ ). Obviously both switches are subject to switching losses as well as substantial conduction losses at a large modulation index and unity power factor. In contrast, the inner switches (T1 and 2Τ ) cause only conduction losses at this operating point. Since there are no conduction and switching losses in the inverse diodes, the sum of conduction and switching losses and thus the junction temperatures of the NPC diodes (D2, D1) are larger than those of the inner inverse diodes (
1 2T TD ,D ).
Figure 6-12 Average junction temperature of IGBTs and diodes (Udc,n = 6118V, ma = 1.15, cosϕ
6.1.4. Comparison of 4.16kV, 4.32MVA Multi-Level Converters at Constant Efficiency The conditions for the fourth aspect of comparison are a constant converter efficiency of about 99% at a constant converter power of SC = 4.32MVA, assuming a line-to-line voltage of 4.16kV. To compare the converter switch utilization of the three-level topologies (i.e. the 3L-NPC VSC and 3L-FLC VSC), 6.5kV IGBTs/diodes and a series connection of two 3.3kV IGBTs/diodes are considered. Table 6-5 summarizes the design of the power semiconductors while assuming a carrier frequency of fC = 450Hz in all topologies.
In a second step, the carrier frequencies, the ideal rated IGBT/diode currents, and thus the installed switch powers were determined in an iterative simulation procedure to achieve both the efficiency requirement (η ≈ 99%) at the specified converter power and a junction temperature of
L L R R L L R RT T T T D D D D
2 1 1 2 2 1 1 2T T T TT T T T D D D D
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8 0
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2 1 2 1 2 1 2 1 2 1T T T TT T T T D D D D D D0
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3 2 1 1 2 3 3 2 1 1 2 3T T T T T TT T T T T T D D D D D D0
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124 CONVERTER COMPARISON
Tj,max = 125°C at one worst case operating point [25], [29]. Table 6-6 depicts the resulting ideal rated currents, installed switch powers, and carrier frequencies.
The 3L-NPC VSC is used as a reference. Figure 6-13b shows the efficiencies as a function of the phase current. It is remarkable that the efficiency of the 3L-NPC VSC (fC = 450Hz) is higher and that there are thus smaller losses than in the other topologies in the entire current range.
Table 6-5 Converter voltage and semiconductor specifications for a constant converter power and carrier frequency (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA, fC = 450Hz, Tj,max = 125°C), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Table 6-6 Carrier and harmonic carrier band frequencies, capacity of flying capacitors, and
installed switch power for a converter efficiency of about 99% (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB
Nominal devices voltage 6.5kV IGBT
2x3.3kV IGBT
6.5kV IGBT
2x3.3kV IGBT 4.5kV IGBT 1.7kV IGBT
Nominal devices current 704.4A 748A 768A 638.4A 734.1A 655.7A Converter efficiency η 99.3% 98.95% 98.96% 98.88% 98.99% 98.92% Carrier frequency fC 450Hz 1250Hz 475Hz 650Hz 610Hz 1155Hz Frequency of the first harmonics carrier band f1Cb
450Hz 1250Hz 950Hz 1300Hz 1830Hz 9240Hz
Capacity of the flying capacitors C1,2
- - 1946µF 1422µF 1316µF -
Stored energy of the flying capacitors EC - - 27314J 19960J 41078J -
Installed switch power SS 101.06 MVA
103.67 MVA
60.83 MVA
75.84 MVA
87.41 MVA
79.32 MVA
Relative installed switch power SSR 97.5% 100% 58.7% 73.2% 84.3% 76.5%
Converter line-to-line voltage Ull,rms,1
4.16kV
Dc link voltage Udc,n 6118.5V Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB
Relative installed switch power SSR 122.6% 100% 106.6% 86.7% 100.4% 90.2%
CONVERTER COMPARISON 125
It is furthermore interesting to note that the application of two series connected 3.3kV IGBTs/diodes increases the installed switch power by 2.6% at a 277.8% higher switching frequency, compared to the use of 6.5kV IGBTs/diodes. The distribution of conduction and switching losses (Figure 6-13a) demonstrates that the series connection of 3.3kV IGBTs enables an almost equal share of switching and on state losses for fC = 1250Hz. In contrast, the switching losses of 6.5kV IGBTs cause about two-thirds of the total losses at fC = 450Hz, because these devices are optimized for distinctly lower switching frequencies.
Both on state and switching losses of the 3L-FLC VSC are slightly higher, compared to the 3L-NPC VSC, at an identical frequency of the first carrier band since the ideal current ratings of the switches in the 3L-FLC VSC are distinctly lower due to the better loss distribution [20], [24], [25].
The installed switch powers of the 3L-, 4L-FLC VSCs, and the 9L-SC2LHB VSC are reduced by 41.3%, 15.7%, and 23.5% respectively, in comparison to the 3L-NPC VSC (fC = 1250Hz), applying two series connection of a 3.3kV IGBT/diode (Figure 6-13c). Therefore, unlike the other topologies, the 3L-FLC VSC enables maximum switch utilization (Figure 6-13d). The loss distribution shows an extremely low share of switching losses in the 9L-SC2LHB VSC (Figure 6-13a).
Figure 6-13 Loss distribution (a), efficiency (b), and relative installed switch power (c)
The values of the flying capacitors are depicted in Table 6-6, according to equation (5-5). The stored energy in the flying capacitors of the 4L-FLC VSC is more than the factors of 1.5 (fC = 475Hz) and 2 (fC = 650Hz) and higher than that of the 3L-FLC VSC, which results in substantially higher expenses of capacitors in the 4L-FLC VSC.
The simulated voltage ripple ∆UC and current iC,rms of the flying capacitors are depicted in Figure 6-14 and Figure 6-15 as functions of the modulation index ma and the phase shift ϕ between the converter output voltage and current for the carrier frequency of fC = 1200Hz [24], [29]. The maximum voltage ripple and current stress of the 3L-FLC VSC occur at a modulation index of ma = 0 (∆UC,max = 460V, iC,max = 600A (see Figure 6-14)), while the maximum voltage ripple of the 4L-FLC VSC occurs at ma = 0.808 and ϕ = 90° (∆UC,max = 589V (see Figure 6-15)). The capacitor current of the 4L-FLC VSC reaches a maximum in the modulation range of 0 < ma < 0.33 independent of ϕ (iC,max = 489A (see Figure 6-15)). The voltage and current ripple of the 4L-FLC VSC are about 29% higher and 18% lower respectively than that of the 3L-FLC VSC [29].
Figure 6-14 Flying capacitor current (a) and voltage ripple (b) of a 3L-FLC VSC as functions of
the modulation index and phase shift (Iph,rms,1 = 600A, fC,3L-FLC = 1200Hz, C = 770µF)
Figure 6-15 Flying capacitor current (a) and voltage ripple (b) of a 4L-FLC VSC as functions of
the modulation index and phase shift (Iph,rms,1 = 600A, fC,4L-FLC = 1200Hz, C1,2 = 518µF)
The harmonic spectra of the line-to-line output voltage of the considered converters are shown in Figure 6-16. The first carrier band of the line-to-line voltage of the 3L-NPC VSC occurs at the carrier frequency of fC = 450Hz using 6.5kV IGBTs. On the other hand, the first carrier band of the line-to-line voltage of the 3L- and 4L-FLC VSCs are increased by a factor of 2 (f1Cb = 950Hz) and 4 (f1Cb = 1830Hz) respectively, compared to the 3L-NPC VSC (Table 6-6). In contrast, the first carrier band of the line-to-line output voltage of the 9L-SC2LHB VSC (f1Cb = 9240Hz) is centred around twenty times the carrier frequency (f1Cb = 20fC) (Figure 6-16). Hence, an output filter of the 9L-SC2LHB VSC could be smaller than the corresponding filters of the other topologies.
Figure 6-16 Harmonic spectrum of line-to-line voltage at constant efficiency (Iph,rms,1 = 600A, fo =
6.2. Comparison of Power Semiconductor Utilization and Loss Distribution for 2.3kV-6kV Multi-Level Converters (3L-NPC VSC and SC2LHB VSCs)
Among the aforementioned medium voltage converters, this section takes only the 3L-NPC VSC and the SC2LHB VSCs into account. The converter output power and the semiconductor utilization are examined at the three different carrier frequencies of 450Hz, 750Hz, and 1050Hz for line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV. Table 6-7 depicts the technical data and conditions of the considered converter topologies.
The loss distribution and the relative installed switch power of the investigated converter topologies are shown in Figure 6-17, assuming the constant carrier frequency (450Hz, 750Hz, and 1050Hz) and a constant phase current (Iph,rms,1 = 600A). It is interesting to note that the 5L-, 7L-, and 9L-SC2LHB VSCs generate higher converter losses than the corresponding 3L-NPC VSCs in the output voltage classes of 2.3kV, 3.3kV, and 4.16kV. In contrast, for a line-to-line output voltage of 6kV, the converter losses of the 11L-SC2LHB VSC are reduced by 8% at fC = 450Hz, 13.2% at fC = 750Hz, and 18.9% at fC = 1050Hz, compared to the 3L-NPC VSCs. The switching losses of the SC2LHB VSCs (5L-, 7L-, 9L-, and 11L) topologies are significantly lower than that of the 3L-NPC VSCs in all considered output voltage classes and carrier
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fC,3L-NPC-6.5kV = 450Hz
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fC,4L-FLC-4.5kV = 610Hz
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fC,3L-FLC-6.5kV = 475Hz
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orm
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fC,9L-SCHB-1.7kV = 1125Hz
Frequency [kHz]
128 CONVERTER COMPARISON
frequencies (for example, 11% for 2.3kV, 39% for 3.3kV, and 59% for 4.16kV, and 6kV at fC = 450Hz), since the 1.7kV IGBTs generate distinctly less switching losses than the 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. On the other hand, the conduction losses of the SC2LHB VSCs occurring at line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV are increased in all considered carrier frequencies, compared to the 3L-NPC VSC topology (16%, 145%, 121%, and 27% at fC = 750Hz).
It is remarkable that the relative installed switch power SSR of the SC2LHB VSCs decreases when increasing the line-to-line output voltage and the carrier frequency (Figure 6-17).
Table 6-7 Power semiconductor design (Iph,rms,1 = 600A, ma = 1.15, cosϕ = 0.9)
Figure 6-17 Semiconductor loss distribution and relative installed switch power occurring at
line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV at the different switching frequencies of 450Hz, 750Hz, and 1050Hz (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cosϕ = 0.9, Tjmax = 125°C), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
For all examined output voltage classes and carrier frequencies, the SC2LHB VSCs enable a minimum installed switch power which is decreased, for example, by 18% for 2.3kV, 38% for
2.3kV 3.3kV 4.16kV 6kV0
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-NPC
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3L-N
PC
2*3.3kV
7L-S
C2L
HB
1.7kV
3L-N
PC
6.5kV
3L-N
PC
2*3.3kV
9L-S
C2L
HB
1.7kV
3L-N
PC
2*6.5kV
3L-N
PC
3*3.3kV
11L-
SC2L
HB
1.7kV
PconTPconDPonTPoffTPoffD
2.3kV 3.3kV 4.16kV 6kV0
20
40
60
80
100
120
140
Rel
ativ
e in
stal
led
switc
h po
wer
[%]
3L-N
PC (3
.3kV
IGB
T)
%100
5L-S
C2L
HB
(1.7
kV IG
BT)
%89
7L-S
C2L
HB
(1.7
kV IG
BT)
%132
3L-N
PC (4
.5kV
IGB
T)
%100
3L-N
PC (2
*3.3
kV IG
BT)
%120
7L-S
C2L
HB
(1.7
kV IG
BT)
%92
3L-N
PC (6
.5kV
IGB
T)
%100
3L-N
PC (2
*3.3
kV IG
BT)
%74
9L-S
C2L
HB
(1.7
kV IG
BT)
%74
3L-N
PC (2
*6.5
kV IG
BT)
%100
3L-N
PC (3
*3.3
kV IG
BT)
%67
11L-
SC2L
HB
(1.7
kV IG
BT)
%56
(a) fC = 450Hz
2.3kV 3.3kV 4.16kV 6kV0
10
20
30
40
50
60
70
Pow
er lo
ss d
istri
butio
n [k
W]
3L-N
PC
3.3kV
5L-S
CH
B
1.7kV
7L-S
CH
B
1.7kV
3L-N
PC
4.5kV
3L-N
PC
2*3.3kV
7L-S
CH
B
1.7kV
3L-N
PC
6.5kV
3L-N
PC
2*3.3kV
9L-S
CH
B
1.7kV
3L-N
PC
2*6.5kV
3L-N
PC
3*3.3kV
11L-
SCH
B
1.7kV
PconTPconDPonTPoffTPoffD
2.3kV 3.3kV 4.16kV 6kV0
20
40
60
80
100
120
Rel
ativ
e in
stal
led
switc
h po
wer
[%]
3L-N
PC (3
.3kV
IGB
T)
%100
5L-S
C2L
HB
(1.7
kV IG
BT)
%84
7L-S
C2L
HB
(1.7
kV IG
BT)
%123
3L-N
PC (4
.5kV
IGB
T)
%100
3L-N
PC (2
*3.3
kV IG
BT)
%105
7L-S
C2L
HB
(1.7
kV IG
BT)
%78
3L-N
PC (6
.5kV
IGB
T)
%100
3L-N
PC (2
*3.3
kV IG
BT)
%64
9L-S
C2L
HB
(1.7
kVIG
BT)
%60
3L-N
PC (2
*6.5
kV IG
BT)
%100
3L-N
PC(3
*3.3
kVIG
BT)
%57
11L-
SC2L
HB
%45
(b) fC = 750Hz
2.3kV 3.3kV 4.16kV 6kV0
10
20
30
40
50
60
70
Pow
er lo
ss d
istri
butio
n [k
W]
3L-N
PC
3.3kV
5L-S
CH
B
1.7kV
7L-S
CH
B
1.7kV
3L-N
PC
4.5kV
3L-N
PC
2*3.3kV
7L-S
CH
B
1.7kV
3L-N
PC
6.5kV
3L-N
PC
2*3.3kV
9L-S
CH
B
1.7kV
3L-N
PC
2*6.5kV
3L-N
PC
3*3.3kV
11L-
SCH
B
1.7kV
PconTPconDPonTPoffTPoffD
2.3kV 3.3kV 4.16kV 6kV0
20
40
60
80
100
120
Rel
ativ
e in
stal
led
switc
h po
wer
[%]
3L-N
PC (3
.3kV
IGB
T)
%100
5L-S
C2L
HB
(1.7
kV IG
BT)
%82
7L-S
C2L
HB
(1.7
kV IG
BT)
%119
3L-N
PC (4
.5kV
IGB
T)
%100
3L-N
PC (2
*3.3
kV IG
BT)
%88
7L-S
C2L
HB
(1.7
kVIG
BT)
%62
3L-N
PC (6
.5kV
IGB
T)
%100
3L-N
PC(2
*3.3
kVIG
BT)
%58
9L-S
C2L
HB
(1.7
kV)
%50
3L-N
PC (2
*6.5
kV IG
BT)
%100
3L-N
PC(3
*3.3
kV)
%51
11L-
SC2L
HB
%38
(c) fC = 1050Hz
130 CONVERTER COMPARISON
3.3kV, 50% for 4.16kV, and 62% for 6kV at the carrier frequency of fC = 1050Hz, in comparison to the corresponding 3L-NPC VSCs (Table 6-7).
Furthermore, the first carrier band of the line-to-line output voltage of the 3L-NPC VSC occurs around the carrier frequency (f1Cb = fC), whereas the first carrier band of the line-to-line output voltage of the 5L-, 7L-, 9L-, and 11L-SC2LHB VSCs are centred around four, six, eight, and ten times the carrier frequency respectively. Hence, an output filter of the SC2LHB VSCs could be smaller than the corresponding filters of the 3L-NPC VSC topology.
6.3. Comparison of the DC Link Capacitor for a 24-pulse, 4.16kV, 4.32MVA, 3L-NPC VSC and 9L-SC2LHB VSC
Comparison of the dc link capacitor for a 24-pulse, 4.16kV, 4.32MVA, 3L-NPC VSC and 9L-SC2LHB VSC is the purpose of this section (refer to Figure 4-1). Design criteria like the dc link voltage ripples and the dc link capacitor storage energy are considered to determine the suitable size of the dc link capacitor.
In a first step, the maximum value of the ripple in the dc link capacitor current is computed, considering the influence of the operating parameters at the inverter mode, e.g. load angle (ϕ = -180…180°) and the modulation index (ma = 0…1.15). Due to capacitor voltage balancing in the 3L-NPC VSC, the dc link capacitors are replaced by constant ideal voltage sources, of which each is one-half of the dc link voltage. A three-phase sinusoidal current source with a constant amplitude of 850A is assumed as a load. Figure 6-18 illustrates the root mean square (rms), average and ripple current at the dc rail of the capacitor bank (according to Figure 3-6 and Figure 3-39) as a function of the modulation index ma and load angle ϕ. They show that the result is symmetrical concerning the axle of the load angle, and the maximum value of the ripple current occurs at ma = 0.6 and ϕ = 0, ±180° in the 3L-NPC VSC (Figure 6-18c) and ma = 1.15 and ϕ = 0, ±180° in the 9L-SC2LHB VSC (Figure 6-18f).
In a second step, to investigate the dc link voltage ripple, the grid, and load currents (according to Figure 4-1) the modulation index of ma = 0.6 (for the 3L-NPC VSC) and ma = 1.15 (for the 9L-SC2LHB VSC) are accepted. The minimum size of the dc link capacitor is determined by using equation (5-3) for the 3L-NPC VSC and equation (5-4) for the 9L-SCHB VSC, applying a voltage ripple of 5%, and equation (5-5), assuming a stored energy of 6J/kVA and 12J/kVA. A standard three-phase symmetric load model was realized by applying a load power factor cosϕ = 0.9 and a machine leakage inductance of LL = 20% (1.37mH). The machine resistance is assumed insignificant.
The system is simulated by a MATLAB program. Figure 6-18Figure 6-19 through Figure 6-28 present the simulation results in the steady state at 100% load for carrier frequency fC = 750Hz.
Figure 6-19 and Figure 6-20 show the grid currents, the transformer primary and secondary winding currents in each 12-pulse transformer, and their harmonic spectrum at a stored energy of 6J/kVA and 12J/kVA for the 3L-NPC VSC respectively. Because of the first dominant utility grid, the phase current harmonics are 23rd and 25th; then the low-frequency harmonic waves are eliminated. The first dominant transformer primary current harmonics are 11th and 13th. The transformer secondary winding currents have harmonic components with low ordinal numbers (h=6k ± 1, where k=1, 2 ...). It is evident that the amplitude of all harmonics are reduced applying a stored energy of 12J/kVA instead of 6J/kVA.
The rectifier output voltage, the rectifier output current, the capacitor voltage ripples, and their harmonic spectrum are depicted in Figure 6-23 and Figure 6-24 at a stored energy of 6J/kVA and 12J/kVA for the 3L-NPC VSC respectively. The results show that the dc link voltage ripple and the dc link current are about 1.3% and 4.96% for the stored energy of 6J/kVA, while they
CONVERTER COMPARISON 131
enable a reduction by 55% and by 47.6% at twice the stored energy.
It is to remark that the dc link voltage ripple of each H-bridge cell of the 9L-SC2LHB VSC is larger than the acceptable value of 5%, assuming a stored energy of 12J/kVA (Figure 6-21, Figure 6-25). Therefore, in order to place the dc link voltage ripple at a permissible limit, an increase in the dc link capacitor by the factor of 2.83 and a recalculation of the stored energy of 34J/kVA are necessary, compared to the stored energy of 12J/kVA (Figure 6-22, Figure 6-26).
Figure 6-27 and Figure 6-28 illustrate the capacitor currents, the output phase-midpoint voltage, the load phase currents, and their harmonic spectrum at a stored energy of 6J/kVA and 12J/kVA respectively. It can be seen that the odd harmonics in the phase-midpoint voltage UaM1 centred around the switching frequency and its multiples.
132 CONVERTER COMPARISON
Figure 6-18 The effective, average, and ripple capacitor current as a function of the modulation
index and load angle in the 3L-NPC VSC according to Figure 3-6: (a-c) (idc2,eff,max/iph,peak = 85.6% at φ = ±180°, 0° and ma = 1.15), (idc2,avg,max/iph,peak = 80.3% at φ = 0° and ma = 1.15), (idc2,rip,max/iph,peak = 45.8% at φ = ±180°, 0° and ma = 0.6), and in the 9L-SC2LHB VSC according to Figure 3-39 (d-f).(idc21,eff,max/iph,peak = 68.7% at φ = ±180°, 0° and ma = 1.15), (idc21,avg,max/iph,peak = 57.5% at φ = 0° and ma = 1.15), (idc21,rip,max/iph,peak = 54.3% at φ = ±90°, and ma = 1.15), (iph,rms,1 = 600A, fC = 750Hz, fo = 50Hz)
(a) (d)
(b) (e)
(c) (f)
CONVERTER COMPARISON 133
Figure 6-19 (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c,
d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
4.88 4.89 4.9 4.91 4.92-200
-100
0
100
200
i s,x
[A]
Time [sec.]
isAisBisC
0 10 20 30 40 5010-2
100
102
Am
plitu
de i
s,x
Harmonics order (a) (b)
4.88 4.89 4.9 4.91 4.92-100
-50
0
50
100
I p1,x
[A
]
Time [sec.]
Ip1UIp1VIp1W
0 10 20 30 40 5010-2
100
102
Am
plitu
de I p
1x
Harmonics order
(c) (d)
4.88 4.89 4.9 4.91 4.92-400
-200
0
200
400
I s,x [
A]
Time [sec.]
Is1,uIs2,uIs3,uIs4,u
0 10 20 30 40 5010-2
100
102
Am
plitu
de I s,
x
Harmonics order (e) (f)
134 CONVERTER COMPARISON
Figure 6-20 (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c,
d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
5.66 5.67 5.68 5.69 5.7-200
-100
0
100
200
i s,x
[A]
Time [sec.]
isAisBisC
0 10 20 30 40 5010-2
100
102
Am
plitu
de i
s,x
Harmonics order (a) (b)
5.66 5.67 5.68 5.69 5.7-100
-50
0
50
100
I p1,x
[A
]
Time [sec.]
Ip1UIp1VIp1W
0 10 20 30 40 5010-2
100
102
Am
plitu
de I p
1,x
Harmonics order (c) (d)
5.66 5.67 5.68 5.69 5.7-400
-200
0
200
400
I s,x [
A]
Time [sec.]
Is1,uIs2,uIs3,uIs4,u
0 10 20 30 40 5010-2
100
102
Am
plitu
de I s,
x
Harmonics order (e) (f)
CONVERTER COMPARISON 135
Figure 6-21 (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC,
(c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
0.18 0.19 0.2 0.21 0.22-200
-100
0
100
200i sx
[A
]
Time [sec.]
isAisBisC
0 10 20 30 40 5010-2
100
102
Am
plitu
de i sx
Harmonics order (a) (b)
0.18 0.19 0.2 0.21 0.22-100
-50
0
50
100
I p1x [
A]
Time [sec.]
Ip1UIp1VIp1W
0 10 20 30 40 5010-2
100
102
Am
plitu
de I p1
x
Harmonics order (c) (d)
0.26 0.27 0.28 0.29 0.3
-500
0
500
I sx [
A]
Time [sec.]
Is1Is2Is3Is4
0 10 20 30 40 5010-2
100
102
104
Am
plitu
de I sx
Harmonics order (e) (f)
136 CONVERTER COMPARISON
Figure 6-22 (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC,
(c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
0.12 0.13 0.14 0.15 0.16-200
-100
0
100
200
i sx [
A]
Time [sec.]
isAisBisC
0 10 20 30 40 5010-2
100
102
Am
plitu
de i sx
Harmonics order (a) (b)
0 0.01 0.02 0.03 0.04-100
-50
0
50
100
I px [
A]
Time [sec.]
Ip1Ip2Ip3
0 10 20 30 40 5010-2
100
102A
mpl
itude
I px
Harmonics order (c) (d)
0.18 0.19 0.2 0.21 0.22
-500
0
500
I sx [
A]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de I sx
Harmonics order (e) (f)
CONVERTER COMPARISON 137
Figure 6-23 (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d):
dc link current and its harmonic spectra, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
2.98 2.99 3
6246
6168
Udc
[V]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
104
Am
plitu
de U
dc
Harmonics order (a) (b)
4.88 4.89 4.9 4.91 4.92280
290
300
310
320
330
i dc [A
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102A
mpl
itude
i d
c
Harmonics order (c) (d)
4.88 4.89 4.9 4.91 4.923030
3107
3184
UCx
[V]
Time [sec.]
UC1UC2
0 10 20 30 40 5010-2
100
102
Am
plitu
de U
Cx
Harmonics order (e) (f)
138 CONVERTER COMPARISON
Figure 6-24 (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d):
dc link current and its harmonic spectra in the 3L-NPC VSC, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
5.68 5.685 5.69 5.695 5.7
6197
6225
Udc
[V]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
104
Am
plitu
de U
dc
Harmonics order
(a) (b)
5.66 5.67 5.68 5.69 5.7280
290
300
310
320
330
i dc [A
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de i
dc
Harmonics order (c) (d)
5.66 5.67 5.68 5.69 5.7
3066
3110
3148
UCx
[V]
Time [sec.]
UC1UC2
0 10 20 30 40 5010-2
100
102
104
Am
plitu
de U
Cx
Harmonics order (e) (f)
CONVERTER COMPARISON 139
Figure 6-25 (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c,
d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
0.26 0.27 0.28 0.29 0.30
200
400
600
800
1000
Udc
HB [
V]
Time [sec.]
UdcHB,1UdcHB,2UdcHB,3UdcHB,4
0 10 20 30 40 50
10-2
100
102
Am
plitu
de U
dc,H
B
Harmonics order
(a) (b)
0.26 0.27 0.28 0.29 0.30
200
400
600
800
1000
i dcx [
A]
Time [sec.]
idc1idc2idc3idc4
0 10 20 30 40 50
10-2
100
102A
mpl
itude
Udc
,HB
Harmonics order (c) (d)
0.26 0.27 0.28 0.29 0.3
-3000
-2000
-1000
0
1000
2000
3000
Uan
[V
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de U
an´
Harmonics order (e) (f)
140 CONVERTER COMPARISON
Figure 6-26 (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c,
d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
0.26 0.27 0.28 0.29 0.30
200
400
600
800
1000
Udc
HB [
V]
Time [sec.]
UdcHB,1UdcHB,2UdcHB,3UdcHB,4
0 10 20 30 40 50
10-2
100
102
Am
plitu
de i dc
,x
Harmonics order
(a) (b)
0.26 0.27 0.28 0.29 0.30
200
400
600
800
1000
i dcx [
A]
Time [sec.]
idc1idc2idc3idc4
0 10 20 30 40 50
10-2
100
102A
mpl
itude
i dc,x
Harmonics order
(c) (d)
0.26 0.27 0.28 0.29 0.3
-3000
-2000
-1000
0
1000
2000
3000
Uan
[V
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de U
an´
Harmonics order (e) (f)
CONVERTER COMPARISON 141
Figure 6-27 (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC,
(c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
5.66 5.67 5.68 5.69 5.7
-500
0
500i C2
[A]
5.66 5.67 5.68 5.69 5.7
-500
0
500
i C1 [A
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de i C
2
Harmonics order
(a) (b)
4.88 4.89 4.9 4.91 4.92
-3000
-2000
-1000
0
1000
2000
3000
UaM
1 [V]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
104
Am
plitu
de U
aM1
Harmonics order
(c) (d)
4.88 4.89 4.9 4.91 4.92-1000
-500
0
500
1000
i L,x [
A]
Time [sec.]
iLaiLbiLc
0 10 20 30 40 5010-2
100
102
Am
plitu
de i
L,x
Harmonics order (e) (f)
142 CONVERTER COMPARISON
Figure 6-28 (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC,
(c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cosφ = 0.9)
5.66 5.67 5.68 5.69 5.7
-500
0
500i C2
[A]
5.66 5.67 5.68 5.69 5.7
-500
0
500
i C1 [A
]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
Am
plitu
de i C
2
Harmonics order
(a) (b)
5.66 5.67 5.68 5.69 5.7
-3000
-2000
-1000
0
1000
2000
3000
UaM
1 [V]
Time [sec.] 0 10 20 30 40 50
10-2
100
102
104
Am
plitu
de U
aM1
Harmonics order
(c) (d)
5.66 5.67 5.68 5.69 5.7-1000
-500
0
500
1000
i L,x [
A]
Time [sec.]
iLaiLbiLc
0 10 20 30 40 5010-2
100
102
Am
plitu
de i
L,x
Harmonics order (e) (f)
7. CONCLUSION AND DISCUSSION
In this thesis, different multi-level converters (the 2L-VSC, 3L-NPC VSC, 3L-, 4L-FLC VSCs, SC2LHB VSCs, and SC3LHB VSCs) have been investigated in terms of the feasibility of their utilization in medium voltage applications. The medium voltage drives in the 2.4MVA to 6.2MVA range with voltage ratings from 2.3kV to 6kV have been studied, applying 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBT modules. The modelling of the converter has been derived and the principles of operation that include the structure, the design of the power semiconductor devices and passive components, the design of the dc link capacitor, and the function of the multi-pulse isolation transformer have been discussed. To evaluate the converter topologies for a variety of applications, three commercially available MV topologies (i.e. the 3L-NPC VSC, FLC VSCs, and SC2LHB VSCs) have been compared in detail and the simulation results (regarding the converter losses, the semiconductor loss distribution, the efficiency, the installed switch power, and the harmonic spectrum) have been investigated, assuming a maximum junction temperature of Tj,max = 125°C at a phase current of Iph,rms,1 = 600A and a carrier frequency of fC = 450Hz...1050Hz.
In the first comparison, a constant carrier frequency fC and a constant installed switch power SS (which is a measure for the expense of semiconductors) have been examined to compare the maximum converter output power SC,max and the semiconductor utilization of the considered converter topologies. The simulation results show that the SC2LHB VSCs provided the maximum converter output power SC,max in all investigated line-to-line output voltage classes. The switching losses of the SC2LHB VSC topologies were significantly lower than those of the other topologies in all considered output voltage classes, since the 1.7kV IGBTs generate distinctly less switching losses than other IGBTs at their corresponding commutation voltage. An output filter of the SC2LHB VSCs could be smaller than the corresponding filters of other topologies due to the first carrier band of the line-to-line output voltage of the 5L-, 7L-, 9L-, and 11L-SC2LHB VSCs being centred around four, six, eight, and ten times the carrier frequency. The weighted total harmonic distortion WTHD of the 11L-SC2LHB VSC was significantly lower than that of other topologies due to the eleven-level characteristic of its output voltage.
In the second comparison, a constant installed switch power SS as well as an equal output current (Iph,rms,1 = 600A) and a constant converter output power SC with line-to-line output voltages of 2.3kV, 3.3kV, and 4.16kV have been assumed to calculate the maximum carrier frequency fC,max of the considered converter topologies. The simulation results illustrate that the SC2LHB VSCs realized a higher maximum carrier frequency than that of all investigated topologies for all the considered line-to-line output voltages. Moreover, the first carrier band f1Cb of the line-to-line output voltage of the 5L-, 7L-, and 9L-SC2LHB VSC occurred around 6.34kHz, 7.8kHz, and 27.6kHz at fC = 450Hz, and 12.2kHz, 31.5kHz, and 61.6kHz at fC = 1000Hz respectively. Thus, for all considered output voltage classes, the SC2LHB VSCs could enable the smallest sine output filters, compared to other topologies. When comparing the WTHD at the maximum possible carrier frequency, the 9L-SC2LHB VSC featured the minimum value, since the harmonics of the first carrier band (f1Cb = 27.6kHz at fC = 450Hz, and f1Cb = 61.6kHz at fC = 1000Hz) are strongly damped.
The conditions for the third comparison were the constant installed switch power SS as well as the constant frequency of the first harmonic carrier band f1Cb, which enables the design of an
144 CONCLUSION AND DISCUSSION
output filter of about the same size and cost. To place the first harmonic carrier band at the frequency occurring in the 3L-NPC VSC (f1Cb = fC = 450Hz / 1000Hz), the carrier frequencies of the different topologies have been reduced. The maximum apparent converter output power SC,max of the 5L-, 7L-, and 9L-SC2LHB VSCs have been increased by 15%, 10.5%, and 37% at fC = 450Hz and by 34.3%, 74.3%, and 119.4% at fC = 1000Hz, in comparison to the 3L-NPC VSC in the corresponding output voltage classes of 2.3kV, 3.3kV, and 4.16kV. In comparison to the corresponding 3L-NPC VSC topologies, the switching losses of the 5L-, 7L-, and 9L-SC2LHB VSCs were significantly lower due to using the 1.7kV-IGBTs (for example, by 76% for 2.3kV, by 88% for 3.3kV, and by 94% for 4.16kV at fC = 450Hz), while their conduction losses were increased (for example, by 5% for 2.3kV, by 118% for 3.3kV, and by 70% for 4.16kV at fC = 450Hz). Both the THD and the WTHD of the 9L-SC2LHB VSC were still the smallest, since the distortion of the output voltage was at a minimum due to the applied nine-levels (fC = 450Hz).
The conditions for the fourth comparison were a constant converter efficiency of about 99% at a constant converter power of SC = 4.32MVA, assuming a line-to-line voltage of 4.16kV for a medium switching frequency of fC = 450Hz in all considered topologies.The efficiency of the 3L-NPC VSC at fC = 450Hz was higher and there were thus smaller losses than in the other topologies. The comparison of 6.5kV IGBTs/diodes and a series connection of two 3.3kV IGBTs/diodes per switch position in a (4.16kV, 4.32MVA) 3L-NPC VSC and a 3L-FLC VSC shows that 3.3kV IGBT modules enable a substantially higher converter switch utilization and efficiency in the examined switching frequency range of fC ≥ 1kHz [29]. The application of a series connection of two 3.3kV IGBT/diode increased the installed switch power by 2.6% at a 277.8% higher switching frequency, compared to the use of 6.5kV IGBTs/diodes. The distribution of conduction and switching losses demonstrates that the series connection of 3.3kV IGBTs enable an almost equal share of switching and on state losses for fC = 1250Hz. In contrast, the high share of switching losses of 6.5kV IGBTs cause about two-thirds of the total losses at fC = 450Hz and a reduction of the installed switch power, because these devices are optimized for distinctly lower switching frequencies. A maximum first carrier band frequency of f1Cb = 900Hz can be achieved by supposing an installed switch power of SS = 101.06MVA. The unsymmetrical loss distribution within the 3L-NPC VSC [19], [28], [29], [119] and the additional neutral point clamp diodes are the reason for the 3L-NPC VSC requiring the highest installed switch power among the different ML topologies. In comparison to the 3L-NPC VSC, the installed switch powers of the FLC VSCs are reduced and the maximum first carrier band frequencies of the 3L-FLC VSC as well as 4L-FLC VSC are increased. However, both of the FLC VSCs required a substantial expense of flying capacitors at low and medium switching frequencies. Therefore, the flying capacitor topology is not competitive in applications that require only low and medium switching frequencies (f1Cb ≤ 1500-1800Hz) [29]. Still, the symmetrical semiconductor loss distribution and the resulting high first carrier band frequency of the converter voltage make this topology attractive for high speed drives or applications with very low current ripple requirements (e.g. test benches) [29]. The 9L-SC2LHB VSC requires a lower installed switch power than the 3L-NPC VSC (by 23.5% at fC = 1250Hz, applying two series connection of a 3.3kV IGBT/diode). Furthermore, an extremely low share of switching losses and an extraordinary high maximum first carrier band of the line-to-line output voltage of the 9L-SC2LHB VSC (f1Cb = 9240Hz) can be achieved at a given installed switch power. Hence, an output filter of the 9L-SC2LHB VSC could be smaller than the corresponding filters of other topologies.
When taking only the 3L-NPC VSC and the SC2LHB VSCs into account, the 5L-, 7L-, and 9L-SC2LHB VSCs generate higher converter losses than the corresponding 3L-NPC VSCs in the output voltage classes of 2.3kV, 3.3kV, and 4.16kV, assuming a constant carrier frequency
CONCLUSION AND DISCUSSION 145
(450Hz, 750Hz, and 1050Hz) and a constant phase current (Iph,rms,1 = 600A), while the converter losses of the 11L-SC2LHB VSC are reduced by 8% at fC = 450Hz, 13.2% at fC = 750Hz, and 18.9% at fC = 1050Hz, compared to the 3L-NPC VSCs for a line-to-line output voltage of 6kV. Furthermore, the switching losses of the SC2LHB topologies are significantly lower (11%, 39%, 59%, and 59% at fC = 450Hz) than those of the 3L-NPC VSCs in all considered output voltage classes (2.3kV, 3.3kV, 4.16kV, and 6kV) and carrier frequencies (450Hz, 750Hz, and 1050Hz), whereas the conduction losses of the SC2LHB VSCs are increased in all considered carrier frequencies and output voltage classes (16%, 145%, 121%, and 27% at fC = 750Hz). Thus, for all examined output voltage classes and carrier frequencies, the SC2LHB VSCs enable a minimum installed switch power, which is decreased, for example, by 18% for 2.3kV, 38% for 3.3kV, 50% for 4.16kV, and 62% for 6kV at the carrier frequency of fC = 1050Hz.
In the last section, the dimensioning of the dc link capacitor has been investigated for a 24-pulse, 4,16kV, 4.32MVA, 3L-NPC VSC and the 9L-SC2LHB VSC, assuming the dc link voltage ripples of 5% and the dc link capacitor storage energy of 6J/kVA and 12J/kVA at fC = 750Hz. The simulation results show that the maximum value of the ripple current occurred at modulation index ma = 0.6 and load angle ϕ = 0, ±180° for the 3L-NPC VSC, and ma = 1.15 and ϕ = ±90° for the 9L-SC2LHB VSC. It is to remark that the dc link voltage ripple and the dc link current are about 1.3% and 4.96% for the stored energy of 6J/kVA, while they enable a reduction by 55% and by 47.6% at twice the stored energy for the 3L-NPC VSC. Furthermore, the dc link voltage ripple of each H-bridge cell of the 9L-SC2LHB VSC is larger than the acceptable value of 5%, assuming a stored energy of 6-12J/kVA. Therefore, in order to place the dc link voltage ripple at a permissible limit, an increase in the dc link capacitor by the factor of 2.8 and a recalculation of the stored energy of 34J/kVA are necessary, compared to the stored energy of 12J/kVA.
In conclusion, the 3L-NPC VSC is a competitive and widely used topology for a large variety of low and medium switching frequency applications (e.g. fC ≤ 1500Hz) in a voltage range of 2.3kV ≤ V
ll ≤ 4kV [29]. A simple grid transformer, a small dc link capacitor, and the possible
modular realization of common dc bus configurations are attractive additional features of this topology [119]. However, for the more than three-level configuration, the NPC voltage imbalance problem cannot be overcome by utilizing control techniques. Therefore, an increase of the output voltage of the 3L-NPC-VSC requires the use of the series connection of commercially available 3.3kV-6.5kV IGBTs or IGCTs or development of new devices with increased blocking voltages (e.g. 10kV IGCTs) [28].
is makes the NPC unsuccessful in high voltage applications. To synthesize the same number of voltage levels, the SC2LHB requires the least number of total main components. Another dominant advantage of the SC2LHB is its circuit layout flexibility. Each level has the same structure and there are no extra clamping diodes or voltage balancing capacitors, which are required in the NPC and the FLC topologies. The number of output voltage levels can then be easily adjusted by changing the number of H-bridge cells. Moreover, redundancy can be easily applied to enhance the reliability of the entire system. The high converter switch utilization, the high maximum carrier frequencies, and the low total harmonic distortions of the converter voltage and current are attractive features of the SC2LHB VSC topology, compared to the 3L-NPC VSC which is widely used in MV applications today. The modular topology structure of the SC2LHB enables a simple extension of the converter voltage range to Ull,rms,1 > 4kV [29]. However, the high number of semiconductors, a complex and expensive multi-pulse isolation transformer, increased dc link capacitance values and the absence of a common dc voltage bus are disadvantages of this topology [29], [119]. Overall, the SC2LHB VSC is an attractive topology for manifold MVDs, including high speed drives [29].
APPENDIX A
A.1. MODULATION METHOD There are different PWM methods which have been extended for the use in H-bridge converters by using multiple carriers. These methods are described in many publications in the technical literature [26-32]. They can be categorized into three groups: Phase Shifted (PS), which is linked to FLC VSC and SCHB VSCs, Carrier Disposition (CD), which is used for NPC VSC, and Hybrid (H) methods. The following subsections describe these methods.
I. Phase Shifted (PS) Method This PWM method uses four carrier signals of the same amplitude and frequency, which are phase shifted by TC/4, where TC is the period of the carrier signal. The modulation method for a 5-level H-Bridge is shown in Figure A-2a.
II. Carrier Disposition (CD) Methods This carrier disposition can be classified into the following three methods, which are usually applied to the neutral point clamped topology [33], [34]. These methods may not be used naturally for the H-Bridge converter applications. However, an implementation strategy has been suggested to apply PD method to the H-Bridge converter [31], which uses discontinuous PWM reference signals with phase-shifted carriers.
1. Phase Disposition (PD) Method: This PD method has all carrier waveforms in phase, as shown in Figure A-2b. The zero reference is placed in the middle of the carrier sets.
2. Phase Opposition Disposition (POD) Method: With the POD method the carrier waveforms above or below the zero reference value are in phase. However, they are phase shifted by 180° between the carrier waveforms above and below zero, as shown in Figure A-2c.
3. Alternative Phase Opposition Disposition (APOD) Method: All carrier waveforms in this APOD method are phase-displaced by 180° alternatively, as shown in Figure A-1d.
III. Hybrid (H) method This method is the combination of the PS and CD methods [30], [35]. Figure A-2e shows a triangular carrier, which is divided into a set of carrier signals. The gate signal of one switch is determined by the comparison of this set of carrier signals and the reference signal. The gate signals for the remaining switches are generated by phase shifting the set of carriers by TC/4 of the carrier set frequency.
IV. Space vector method The space vector modulation (SVM) is based on the description of symmetrical three-phase systems in the α-ß reference frame. The three-phase reference voltages are represented as a single reference phasor with constant length and angular speed. It substitutes the demanded voltage space vectors by the nearest real voltage space vectors in an appropriate combination in each sampling interval. The basic principles of the SVM are shown in Figure A-1 for three-level converters, which involves 27 different converter switch states (= number of level)3.
148 APPENDIX A
A.2. Output Waveforms and Spectrum The line-to-line output voltage waveform of the 5L-H-Bridge VSC is depicted in Figure A-2 (e-i) for different PWM methods. The spectra of the line-to-line output voltage waveforms are depicted in Figure A-3 at 1 15am .= and 15fm = for different PWM methods.
Compared to the PWM modulation method for an 5L-H-Bridge converter, the CD methods have unbalanced switch utilization, dependent on am , and the first carrier band of the line-to-line voltage centred around in the carrier frequency. In contrast, the PS method offers a balanced switch utilization and simple implementation. The first carrier band of the line-to-line voltage for the PS and H methods is centred around four times the carrier frequency. Although, the H method has the same switch utilization as the PS method, it is the most complex to implement.
Figure A-1 Space vector modulation of three-level converters
-++ +--
+0-
++ -0+--+-
-+0
-0+
--+ 0-+ +-+
+-0
0--+ 00
00 -++ 0
-0-0 +0
-000 ++
--000 +
0-0+0 +
---000+++
+0--+0
-0+
0-+ +-+
+-0
0--+ 00
00 -++ 0
-0-0 +0
-000 ++
--000 +
0-0+0 +
Vref---000+++
α
β
APPENDIX A 149
Figure A-2 Different PWM methods and their line-to-line output voltage waveforms of the 5L-H-
Bridge VSC
Udc / 2
Udc
-Udc
0
-Udc / 2
Udc / 2
Udc
-Udc
0
-Udc / 2
Udc / 2
Udc
-Udc
0
-Udc / 2
Udc / 2
Udc
-Udc
0
-Udc / 2
Udc
2Udc
-2Udc
0
-Udc
Udc
2Udc
-2Udc
0
-Udc
Udc
2Udc
-2Udc
0
-Udc
Udc
2Udc
-2Udc
0
-Udc
0 90° 180° 0 180° 360°
Udc / 2
Udc
-Udc
0
-Udc / 2
Udc
2Udc
-2Udc
0
-Udc
POD POD
PDPD
PSPS
APODAPOD
H H
(a)
(b)
(c)
(d)
(e)
(e)
(f)
(g)
(h)
(i)
150 APPENDIX A
Figure A-3 Harmonic spectra of the line-to-line output voltage for the 5L-H-Bridge VSC
1 mf 2mf 3mf 4mfHarmonic Order
( )ab h
dc
UU
10-2
10-1
100
mf = 15, ma = 1.15
Har
mon
ic M
agni
tude
(p.u
.)
100
100
100
100
10-1
10-1
10-1
10-1
10-2
10-3
10-2
10-2
10-2
0.005
APOD
(a)
(b)
(c)
(d)
(e)
H
POD
PD
PS
mf = 15, ma = 1.15
mf = 15, ma = 1.15
mf = 15, ma = 1.15
mf = 15, ma = 1.15
( )ab h
dc
UU
( )ab h
dc
UU
( )ab h
dc
UU
( )ab h
dc
UU
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