Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 1 of 35 – Prof. Dr. Uwe...

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 1 of 35 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

Part 4

Fundamentals in Computer Technology

Computer Architecture

Slide Sets

WS 2012/2013

Prof. Dr. Uwe BrinkschulteM.Sc. Benjamin Betting


Technology trends: things are getting smarter


Technology trends: networked systems of the future

NetworkedSystems

pervasive computingdisappearing computer

ambient intelligence

ubiquitous computing


Technology trends:heterogeneous hardware-software-systems (HW/SW)

System on Chip Processor-Core, FPGA, RF,Bluetooth ... + Software

Heterogeneity also in the environment (application)


Technology trends:cyber physical systems (CPS)

Integration of physical systems and networked computing

In classical embedded systems, the physical environment is controlled by the computer

In cyber physical systems, the physical environement and the computer(s) closely interact and cooperate

Examples: power grids, networks of autonomoues vehicles, air traffic control, …


System-on-Chip

ASICRF

ADC

DataLink

Memory

DSP CPU

AMP

DAC

Clk

Power Management

Communication

Antenna

Sensor

Cable

Control

Video

Audio

Transmitter

Power

RF

ADC

DataLink

Memory

DSP CPU

AMP

DAC

Clk

Power Management

Bus / InterfaceSensors

Control

Video

Audio

Transmitter

Power

Physical Interfaces

BinaryInterfaces

FPGA/FPFAASIC

RF

ADC

DataLink

Memory

DSP CPU

AMP

DAC

Clk

Power Management

Communication

Antenna

Sensor

Cable

Control

Video

Audio

Transmitter

Power

RF

ADC

DataLink

Memory

DSP CPU

AMP

DAC

Clk

Power Management

Bus / InterfaceSensors

Control

Video

Audio

Transmitter

Power

Physical Interfaces

BinaryInterfaces

FPGA/FPFA

System on Chip (SoC)Functional and technology aspects

Technology Aspects: → Process Combinations necessary

Analog/Digital Systems: → Components, Interfaces + Technologies


A

AD/DA

AD/DA

AD

/DA

AD

/DA

D

An analog component with a digital processor coreEmbedded digital processors are mainly used in analog environments. Life science andtechnical applications are mainly analog. Therefore, an analog to digital conversion andvice versa is necessary.


Microprocessor

Important component of allmodern analog and digitalapplications.

It became the basic measurefor the technological progressin VLSI.

It became the workhorseof all modern ITapplications


Modern processor chips

Intel Pentium Processor

System-on-Chip(Bluetooth SoC: Eynde et al., Alcatel, 2001)

Analog Devices ADSP 21060

Intel Pentium IV IBM Power PC 750

Microphotographs of processor chip layout

Altera FPGA with ARM-core


4004

8080

8086

8028680386

80486

P III

1M

10M

100K

10K

1975 1980 1985 1990 1995 2000

Pentium™

2005 2010

100M

1000 M

P IVCMOSstill state of the art

The Moore curve#

tran

sist

ors

This prediction of Gordon Moore demonstrates the progress of technology in the lastdecades. The complexity of integrated circuits (VLSI) doubles every 18 month.

year

Silicon will be the basic material for the next years.

Core 2

Core i7


The scaling (c)

1999 2001 2003 2005 2008 2011 2014

0,05

0,1

0,15

0,2

year

2000 0,182001 0,182002 0,132003 0,132004 0,132005 0,12008 0,072011 0,032014 0,01

Strukture size[µm]

The area scales with c2

Signal delay of active components scales with c

Signal delay of passivecomponents will be nearly constant

Signal delays are dominatedby the delay of the wires(passive components)

wire-centered design insteadof only logic optimized designor better a combination of both

Structuresize [µm]

c

year


A top down look at computer technology

Architecture Level

Microarchitecture Level

Register Transfer Level

Gate Level

Transistore Level

Charge Level

…



Computer

Architecture Level

Instruction Set Architecture, Memory Sizes, Clock Frequency, …



Computer

Microprocessor, CPU

control unitfunctional unit

(datapath)

memory(program, data)

input/output

connection (bus)

Microarchitecture Level



Register Transfer Level

state register

nextstate

outputfunction

control unit

instruction(program)

data register

functionalunits

data in

data path

datapath

control

CPU


functional unit


Gate Level

&

&

1

1 e 1

e 2

e 3

a

3

0

0

0

1

10

0

00

00

0

1

1

1

11

1



Transistor Level



Charge Level


Planar process technology

Passivation (field oxide)

oxide 4

oxide 3

oxide 2

oxide 1

substrate

metal layer 3

metal layer 2metal layer 2

metal layer 1

Polysilicon

transistor

capacitancemetal to

substrate

capacitancemetal to

metal

oxide = SiO2

Delay times


Modeling of signal delays in wires for the connection of active components (gates) in chip-layouts

Voltage at node nj for a given input voltage UE

)()(1 1

n

j

j

ii

jjEn Rdt

duCUtU

Delay td at node n:

n

j

j

ijji

t

nE uCRdttUUd

1 10

))((

Solution: Approximative solution of the differential equation

2

)1(00

nnCRtd for Ri = R0 Vi Ci= C0 Vi per 1 µm of wire length

current through thecapacitance at node j

RnR1 R2

UE C1 C2Cn

un

DifferentialEquation:

Wire:

Model:

1µm 1µm

Total resistanceat node j

Delay times


Typical values for resistance, capacitance and the resulting delay times for integrated wires

tdD 6,3RD 7CJN 1,8n-diffusion

tdP 1,3RP 17CPF 0,15polysilicon

tdm 0,001RM 0,02CMF 0,1metal

delay time ns

per 1mm 3µm

resistance

/µm

capacitance

fF/µm


300 Ω 300 Ω 300 Ω

R1 R2 R3

measure point 1 measure point 2 measure point 3 measure point 4

UE

C1 C2 C3350fF 350 fF 350 fF

Example of a real wire model


Plot of the node voltage at different measure points per wire length

measure point 1

measure point 2

measure point 3

measure point 4

measure point 4

measure point 3

measure point 2

measure point 1

4,0 V

2,0 V

0 V0 ns 2 ns 4 ns 6 ns 8 ns 10 ns


The clock

Example:- 10 GHz clock frequency (0,1 ns clock period) - 30 mm distance between two components means 10 clock cycles on the wire (silicon)

The clock skew in this exampleis 1 ns. It is too high for sequentialsynchronous circuits.

The clock skew has to be considered in the design phaseand /or has to be avoided byarchitectural solutions.(clock tree, wave pipelining, etc.)

The increasing size of modern chips (chip area) means, that also the connections between the components on the chip become longer.


Memory gap

wirecapacity memory

capacity

memory transistor

Typical design of a DRAM cell

Access time is dominated by charging and decharching of the memory capacity:

ta = Rtransistor Cmemory capacity

C is limited above 10 fF to avoid data loss by alpha particles

R is limited by the area of the memory transistor

=> ta is limited


Memory gap

The memory capacity scales tothe square with the size of thechip

As seen before, access time doesunfortunately not scale this way

Therefore a memory gap exists.

Increasing clock speed generatesan increasing memory gap.

Caches are a good solution but theycan bridge the gap only unsufficientbecause of the limited locality of typical programs.

Because of the memory gap, anincreasing clock speed results notautomatically in a higher execution-speed of programs.

Memory

CPU

memorygap


Unbalanced von Neumann

CPUcaches, ...

vN bottleneck

Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 28 of 35 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt

Reduction of power and energy consumption is a big issue today

On high end systems, heat dissipation has to be reduced

Modern mobile embedded systems need the reduction to increase battery lifetime

=> Tradeoff between high performance and low power/energy consumption

Main ways to reduce power and energy consumption

Reduction of clock frequency Reduction of supply voltage Optimization of microarchitecture

Power consumption


Power consumption and clock frequency

As seen before, CMOS only consumes power when switching

Therefore, in modern gate technologies the energy consumption is mostly proportional to the clock frequency

P ~ f

Reduction of clock frequence means reduction of power consumption,

but as well a reduction of the system performance


The power supply voltage

The power supply voltage cannot easily be reduced under 1-0,5 V.

1999 2001 2003 2005 2008 2011 2014

voltage High Performance [V]

voltage Low Power [V]

0,5

1,0

1,5

year

1999 1,8 1,52000 1,8 1,52001 1,5 1,22002 1,5 1,22003 1,5 1,22004 1,2 0,92005 1,2 0,92008 0,9 0,62011 0,6 0,52014 0,6 0,3

Voltage High

Performance [V]

Voltage Low Power

[V]

year

The reduction of supply voltage implies a reduction of max. clock frequency.

P ~ U2


Possible approaches:

• Reduction of external bus activities (stay local)

• Static Power Management (sleep instructions)

• Dynamic Power Management (control unit deactivates non-used parts of the microarchitecture)

• Increase of code density (saves memory space and cycles)

Power consumption and microarchitecture


Example: reducing memorypower consumption

This disadvantage of a good memory hierarchy is a high degree in energy consumption.

The on-chip data - and instruction caches need itself appr. 25 % of the total power of a processor chip.

CPU

kernel instructions

other instructionsInstruction

Cache

KernelMemory

(small and fast)Off-Chip memory

common address space

A cache oriented solution as an example for a power aware microarchitecture.


SIA-Roadmap

1999 340 23,820002001 340 47,620022003 372 95,220042005 408 1902008 468 5392011 536 15232014 615 4308

yearchip area

[mm²]transistors/ chip [Mio]

1999 1250 902000 1486 1002001 1767 1152002 2100 1302003 2490 1402004 2952 1502005 3500 1602008 6000 1702011 10000 1742014 13500 183

yearfrequency

[Mhz]power con-

sumption [W]

1999 2001 2003 2005 2008 2011 2014

chip area [mm²]

transistors/chip [Mio]

frequency [MHz]

power consumption [W]

year


The challenge (limit) of chip technology in the future

The production of chips with layoutstructures in dimensions under 0.1 µmbecame very difficult with respect tolithography.

Therefore, only about 10% of today’s chips are produced using latest technology

Chips of more than 300 mm2 chip areawill include one or more faults in average, caused only by the technologyprocess.

Increasing cost of chipproduction

$

Decreasing yield of chipproduction


0,001

0,01

0,1

1

10

100

1000

10000

100000

1000000

1975 1980 1985 1990 1995 2000 2005 2010

Bandwidth in Byte/s

Clock in MHz

Tape/Disk in MByte

OS in kByte

Memory in MBit

Design in MTrans.

Development of different parameters incomputer architecture in the past

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Hier wird Wissen Wirklichkeit Computer Architecture – Part 4 – page 1 of 35 – Prof. Dr. Uwe...

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